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Original question:

DS90UB941AS-Q1: Customer need ASIL B for DS90UB941AS-Q1 and TPS1H100A-Q1

DS90UB941AS-Q1: DS90UB941AS-Q1 and 948 I2C issue

Betty Guo
Expert 7300 points

Part Number: DS90UB941AS-Q1

Hi team,

customer use SOC+941+948(MCU)+dispaly

we face a issue is that after SOC init to 941, 941 will sent PWM via I2C to 948 to control display diming. At this time the MCU is initializing 948. Does this will cause LOCK of 948 to low?

Can 948 receive I2C data from 941 and MCU at the same time? customer found the LOCK of 948 is pull low in this condition?

do you have any suggestions about this application?

my understanding for LOCK ,if 941 have a stable clock to 948, it should be high, why I2C can affect it?

thank you

  • 0
    TI__Intellectual 1905 points

    Hi Betty,

    Let me look into this and I will get back to you by early next week.

    Best Regards,

    Solomon

  • 0 in reply to Solomon Ali
    TI__Intellectual 1905 points

    Hi Betty,

    Re: "Can 948 receive I2C data from 941 and MCU at the same time?"

    In the case of accessing 948 registers using the latest generation of FPD-Link III devices (DS90UB94x-Q1), it may be accessed simultaneously from both local and remote I2C masters (948 is acting here as a slave in both directions). These devices have internal logic to properly arbitrate between sources to allow proper read and write access without risk of corruption.

    However, it is not supported to have 948 in the Master mode for 941 I2C communication with another local slave device while in the same time  be in the Slave mode for communication with MCU. Having 948 in both Master and Slave modes at the same time is not supported. If this is required, some method of transferring control between I2C masters should be implemented, such as using GPIOs.

    Re: "customer found the LOCK of 948 is pull low in this condition?"

    Losing LOCK in this case is not expected. Could you share a register dump of both before and after this event occur?

    Best Regards,

    Solomon