DS90UB941AS-Q1: INTB use issue

Sorry, two 948 des.

Hi Arvin,

Thanks for reaching out.

ISR register (0xC7) is a clear on read register. So, upon reading this register by the controller, it will be cleared, which releases INTB pin. If desired, the controller may then read the STS register (0xC4) to determine the current device status. 

So, the question is do you observe INTB pin de-assertion at all before it gets cleared and released by reading reg 0xC7 value?

Regards,

Solomon

Hi Solomon:

      We read reg 0xC7 in the interrupt program , so it wouldn't be cleared before controller get INT signal.

     More info, sometimes we can read interrupt val about reg 0xC7 when plug in the cable, so it's a occasionnal issue.

     Put it another way, if we want use the INTB for LOCK DETECT,  is this configuration ok?

Hi Arvin,

Re: "We read reg 0xC7 in the interrupt program , so it wouldn't be cleared before controller get INT signal."

What event trigger you to read reg 0xC7? Do you read it periodically or you read it when you see INTB goes low?

Re: " More info, sometimes we can read interrupt val about reg 0xC7 when plug in the cable, so it's a occasionnal issue."

Can you explain more what do you mean by "when plug in the cable"? I would be helpful if you can share more details about the working condition vs the case with the issue.

Re: "if we want use the INTB for LOCK DETECT,  is this configuration ok?"

I don't see a problem of using INTB for LOCK detection. We just need to figure out what condition is causing it to not work as expected.

Regards,

Solomon

Hi Solomon:

Re: "We read reg 0xC7 in the interrupt program , so it wouldn't be cleared before controller get INT signal."

What event trigger you to read reg 0xC7? Do you read it periodically or you read it when you see INTB goes low?

[Arvin]: INTB goes low--> Enter interrupt handler --> read reg 0xc7

Re: " More info, sometimes we can read interrupt val about reg 0xC7 when plug in the cable, so it's a occasionnal issue."

Can you explain more what do you mean by "when plug in the cable"? I would be helpful if you can share more details about the working condition vs the case with the issue.

[Arvin]: We're testing the situation cable connection is not tight. And we hope that the host don't need reboot by itself and just do the 948 and 948's slave device's initial work after reinserting the cable.

Hi Solomon:

     Our issue is clear: Why reg 0xC4 has interrupt status(0x28) and reg 0xc7 hasn't val(0x0) at the same time(We don't read yet).  More details to avoid missunderstanding:

1. Power up system(not connect UB948);

2. Insert UB948;

3. Check the log and find system don't received INT(So system have not chance to read register 0xc7 and clear it);

4. Read Regs 0xc4 and 0xc7 by debug tool manually.  Reg 0xC4 has interrupt status(0x28) and reg 0xc7 hasn't 

Hi Arvin,

Thanks for the clarification. 
Let me look into it and I will try to get back to you by the end of this week.

Regards,
Solomon

Hi Arvin,

Could you share register dumps of both 941 (port0 and port1) and the two 948 DESERs when this issue occurs?
I would like to check the value of all other registers when this issue occurs.

Regards,
Solomon