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DP83867IR: RGMII length matching

Part Number: DP83867IR


Hi, 

I have a similar question to DP83867IR: TIDA-00204: Layout RGMII Signals . In EMI/EMC-CompliantIndustrialTempDual-PortGigabitEthernetReferenceDesign it says RGMII signals should be length matched to .254mm, in the answer in the thread I linked the answer is matched within 200ps to the respective clock was mentioned. 200ps would be 30mm. Then the datasheet for the DP83867IR mentions(9.2.2.1.1) that the skew between data signals should be less than 11 ps which is 50mil(1.27mm). Following the most restrictive .254mm causes a lot of serpentine traces since TX_CTL pad is far away from the other TX pads. Our DP83867 is place very close to our processor(AM64x), so overall the traces should be very short, which makes me wonder if excessive length matching is needed. 

I was wondering if I length match the data signals within 1.27mm as per the datasheet, what do the other signals(CLK and CTL) need to be length matched to? Because the two other numbers I have found are .254mm and 30mm which are quite different. Ideally with very short traces length matching to 5-10mm would be relatively easy and be well within the 30mm number but far away from the .254mm number. 

Also is there a length matching requirement between RX and TX groups? Usually we just match the whole RGMII signals, but wondering if we can get away with not doing that since it will make layout easier.

Thanks,

Sam

  • Hi Sam,

    When the 200ps limit is mentioned, it takes into any other potential delay caused by components other than just trace length, thus 30mm would not be a valid assumption. For 1000M speeds, it is recommended to length match traces to 0.5 mm or 20 mils. 

    And, RX and TX do not need to length matched to each other. Only RX signals need to be matched to the other RX signals, and likewise with TX signals.

    Please let me know if this answers your questions and makes sense!

    Thanks,

    Lysny

  • Hi Lysny,

    Thanks for the input

    If I look at the calculations/equations mentioned in SNLA243 the PCBskew variable is 100pS. I am assuming this variable is the PCB skew caused by differences in length matching. This 100pS would equate to 15mm in length matching. Is this the correct interpretation? Also equation 1-4 shows there are 350pS and 200pS of extra setup and hold times respectively which is then said could be used to relax length matching. 

    I guess I am wondering where the .5mm recommendation comes from. Is it a worse case scenario recommendation, and I should feel free to change it if I did the calculations in SNLA243?

    Thanks,

    Sam

  • Hi Sam,

    Like before 100ps cannot be directly translated into a trace length alone. Yes, if you perform these calculations you could potentially relaxed the length matching, but it would be more on the scale of relaxing from 0.5mm to maybe 0.6 or 0.7mm (depending on results). The 0.5mm recommendation comes from high speed data guidelines. I know this is a little vague, but these recommendations are based on various factors that affect signal quality in high speed PCBs. The goal in high speed signal transmissions is to remove as many possible sources of error, so I would recommend sticking as close to the recommendation as possible.

    I hope this helps clear everything up.

    Thanks,
    Lysny