Hi,
I have a similar question to DP83867IR: TIDA-00204: Layout RGMII Signals . In EMI/EMC-CompliantIndustrialTempDual-PortGigabitEthernetReferenceDesign it says RGMII signals should be length matched to .254mm, in the answer in the thread I linked the answer is matched within 200ps to the respective clock was mentioned. 200ps would be 30mm. Then the datasheet for the DP83867IR mentions(9.2.2.1.1) that the skew between data signals should be less than 11 ps which is 50mil(1.27mm). Following the most restrictive .254mm causes a lot of serpentine traces since TX_CTL pad is far away from the other TX pads. Our DP83867 is place very close to our processor(AM64x), so overall the traces should be very short, which makes me wonder if excessive length matching is needed.
I was wondering if I length match the data signals within 1.27mm as per the datasheet, what do the other signals(CLK and CTL) need to be length matched to? Because the two other numbers I have found are .254mm and 30mm which are quite different. Ideally with very short traces length matching to 5-10mm would be relatively easy and be well within the 30mm number but far away from the .254mm number.
Also is there a length matching requirement between RX and TX groups? Usually we just match the whole RGMII signals, but wondering if we can get away with not doing that since it will make layout easier.
Thanks,
Sam
 
				 
		 
					 
                          