DP83848K: the state of each of signal pins during a reset

Hi Daisuke,

I am reaching out for more information on this within my team and will follow up with an update tomorrow!

Thanks,

Lysny

Hi Lysny-san,

Thank you for your support. I am looking forward to your update.

In Figure 5-1 or Figure 5-2 on the data sheet, the dual function pins seems to be in a high impedance state as an input while asserting the RESET_N pin, but that is not clear.

It can not be found the information about any output only pins, any weak internal pull-ups or pull-downs.

Best regards,

Daisuke

Hi Daisuke-san,

Please give me a little longer to find this answer for you! As soon as I have found the information, I will follow up with it on this thread!

Thanks,

Lysny

Hi Lysny-san,

Thank you for your reply.

How is your progress? Have you found any relevant information?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Daisuke-san,

I have been in contact with the team members who would be able to provide this information, but am still waiting on results. I have sent a reminder that you are waiting on this information!

Thank you for your patience,

Lysny

Hi Daisuke-san,

Because this is an older part, we do not have the ability to simulate this information. This info can be found by testing. If you would like me to test it, the earliest I could probably test this information would be at the beginning or middle of next week.

Please let me know how you would like to proceed.

Thanks,

Lysny

Hi Lysny-san,

Thank you for your reply.

I understand you are very busy, but could you test it to find the information?

Best regards,

Daisuke

Hi Daisuke-san,

I will try to test it by the deadline I mentioned. If the customer needs the info sooner, they should be able to test too. I will let you know if anything in my schedule changes.

Thanks,

Lysny

Hi Lysny-san,

Thank you for your support in your busy time.

I am a little confused because you mentioned some of the pins without weak internal pull-up or pull-down.

I understand as follows, is it correct?

All pins without weak internal pull-up or pull-down are high impedance during reset.

All pins with weak internal pull-up or pull-down have the corresponding internal pull-up or pull-down enabled during reset.

All pins do not drive during reset.

Best regards,

Daisuke

Hi Lysny-san,

Thank you for your reply.

I understand as follows:

All signal pins without weak internal pull-up or pull-down are high impedance during reset.

All signal pins with weak internal pull-up or pull-down drain or drive a small amount of current by enabling the corresponding internal pull-up or pull-down during reset.

No signal pins drain or drive a large amount of current during reset.

Is my understanding correct?

Best regards,

Daisuke

Hi Lysny-san,

The reason our customer wants to know the state of each of signal pins during reset is to latch the state of the bootstrap pins of the SoC connected to DP83848K during reset of DP83848K.

If no signal pins drain or drive a large amount of current during reset, our customer will design with the external pull-up or pull-down resistors for the strap pins. If not, they will disconnect the SoC and DP83848K during the reset.

Best regards,

Daisuke

Hi Daisuke-san,

I agree with your understanding of the pin states.

If I may ask a little more about the application, is there a reason that the customer wants to use a SoC to capture the bootstrap pins? If they want more strap on reset information, some of our newer PHYs include that information in the PHY registers.

I would recommend testing the current for your system to determine if it is above or below the required limit for this setup.

Hi Lysny-san,

Thank you for your reply.

Sorry for my poor English.

Our customer does not use a SoC to capture the bootstrap pins of DP83848K. Because the SoC (AMIC110) has its own bootstrap pins which are multiplexed with some of the MII signal pins, the customer wants to know the state of each of pins during reset to latch the SoC's strap pins.

I would recommend the customer to ensure that the current through the pins with internal pull-up or pull-down on both the SoC and DP83848K is within limits.

Best regards,

Daisuke

Hi Lysny-san,

I have additional questions about the current per signal pin.

Each of IIH (Input high current), IIL (Input low current) and IOZ (Tri-state leakage) is 10 uA (MAX) in the DC specifications.

Is each of the signal pins with weak internal pull-up or pull-down also 10 uA (MAX)?

Does the current per signal pin during reset never exceed 10 uA?

Best regards,

Daisuke

Hi Lysny-san,

I'm sorry to post many times. I would appreciate it if you could answer the questions in my previous post.

Our customer is concerned that any output pin may drive instead of tri-state during reset.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Daisuke-san,

My apologies, I was traveling yesterday and did not sync up with what I was working on before I left, after I arrived home. 

Based on the information in the datasheet, I would agree that the max expected current should be 10uA. (But I would still test with the system because the data is not explicitly stated for the reset state)

I would like to add that if there is a strap on the uP and a strap on the PHY that are connected to the same node, they will strap to the same voltage value, if the reset is synchronous. Unless there are components in-between the two, the voltage on the PHY side of the node and the uP side of the node will be the same. 

Does this help?

Thanks and sorry again for the late reply,

Lysny

Hi Lysny-san,

Thank you for your reply.

Could you test to ensure the current per signal pin during reset never exceed 10uA?

If so, how long does it take to update the answer on this thread?

Our customer will prioritize the bootstrap pins on the SoC side over the PHY side. Because most of the settings (except the PHY address) corresponding to the bootstrap pins on the PHY side can be changed by software but most of the settings corresponding to the bootstrap pins on the SoC side cannot be changed by software.

Best regards,

Daisuke

Hi Lysny-san,

Thank you for your reply.

I understand that the 10uA means the maximum current per signal pin, not the sum of all signal pins.

Is my understanding correct?

For the DP83848K, if the maximum current when 3.3V or 0V is applied to each signal pin is 10uA, the minimum impedance of each signal pin is 330kΩ. For the SoC (AMIC110), the maximum leakage current (worst case) is 243uA, so the minimum impedance of each signal pin is 13.58kΩ. An external resistor lower than 4kΩ will be used to change the default strap value for each signal pin.

Best regards,

Daisuke

Hi Lysny-san,

Thank you for your reply. I appreciate your support.

Best regards,

Daisuke