• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 269 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB948-Q1: Screen blink issue

Ryan Wang
Expert 7565 points
Part Number: DS90UB948-Q1


Expert,

The environment is SoC->941->948-> Screen. Screen blink with black&Gray color bar only. Screen is very stable with other color bar. (Blink mean black&Gray color bar brightness keep varying randomly)

We've done below test. The phenomenon is very strange.

With 948 pattern generation(FPDlink disconnected), internal clk or external reference clock, Screen still blink with black&Gray color bar.

With 941 pattern generation, internal 50MHz clk , Screen become quite stable  with black&Gray color bar.

With 941 pattern generation, external ref clock 53MHz ,Screen still blink with black&Gray color bar.

With SoC DSI data, external ref clock 53MHz ,Screen still blink with black&Gray color bar.

Do you have any suggestion for this? Great thanks

  • +1
    TI__Guru** 103215 points

    Hello Ryan,

    I recommend checking this debug guide for step by step instructions on how to diagnose your problem and resolve it when using 941AS: https://www.ti.com/lit/gpn/ds90ub941as-q1 

    Since the pattern works well with internal clock and internal timing patgen, but fails with internal timing/external clock patgen, then it would be best to focus in on the clock portion of the design. Is your 941AS configured for PCLK from DSI clock mode or PCLK from external REFCLK mode? If it is configured for DSI clock mode, then check the DSI clock from the SoC source and make sure that it is continuous (no LP transitions), and that the frequency matches you expectations (for 4 lanes, DSI clock should be PCLK*3). 

    Also I would recommend using the same PCLK value during PATGEN with internal clock/internal timing as you are using when the SoC is the source (53MHz instead of 50MHz) to ensure you are doing a like for like comparison. 

    Best Regards,

    Casey 

  • +1 in reply to Casey McCrea
    TI__Expert 7565 points

    Casey,

    Great thanks for your suggestion. I will further check.