DP83867IR: Can CLK_OUT be set to 125MHz?

Jerry Chen

Part Number: DP83867IR

Hi team,

My customer is using DP83867IRRGZR. Ambarella required that their CV22 processor needs 125MHz clock from CLK_OUT pin for RGMII. How to set CLK_OUT=125MHz? I only saw Reg_0x0170 can set CLK_OUT=transmit clock/receive clock.

Below are the register read for Reg_0x31/32/6e/6f. I see something are disable in Reg_0x32. What are the correct value for these registers?

Thanks.

Reg_0x0000=0x1140

Reg_0x0031=0xac02

Reg_0x0032=0x0000

Reg_0x6e=0xc00

Reg_0x6f=0x3000

over 5 years ago

0 Jerry Chen over 5 years ago

TI__Expert 5110 points

I tried writing Reg_0x170=0x90(Channel B transmit clock), but CLK_OUT is still 25MHz. Should I write in below sequencing? The PHY Linux driver is provided by Ambarella. They didn’t compile our driver successfully.

Write register 0x0D to value 0x001F.
Write register 0x0E to value 0x0170
Write register 0x0D to value 0x401F.
Write register 0x0E to value 0x90

0 Lysny Woodahl over 5 years ago in reply to Jerry Chen

TI__Expert 3595 points

Hi Jerry,

Please help remind me. Did this thread get altered? I have a memory of replying and closing this. Did my reply not post? The 125 MHz clock out is not on this pin. It is on RX_CLK.

+1 Jerry Chen over 5 years ago in reply to Lysny Woodahl

TI__Expert 5110 points

Hi Lysny,

Sorry for deleting your last replay by accident.

CLK_OUT has been set to 125MHz by,

Reg_0x0D=0x001F

Reg_0x0E=0x0170

Reg_0x0D=0x401F

Reg_0x0E=0x90

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DP83867IR: Can CLK_OUT be set to 125MHz?