• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 366 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83848-EP: Power Supply Bulk Capacitor Layout Recommendations

Tanay Ghose
Prodigy 180 points
Part Number: DP83848-EP

The DP83848 has Application Note AN-1469 which covers its layout guidelines. 

In Section 4, it is mentioned that 0.1μF decoupling capacitors should be placed as close as possible to the Vdd pins (the device has 3 - AVDD33, IOVDD33_1 and IOVD33_2). However, for the 10μF bulk capacitor, it is mentioned that it should be placed close to the PHY in general. Is it advised to place the bulk capacitor close to any particular Vdd, say the pin which draws the most current during normal operation ?

  • 0
    TI__Expert 3595 points

    Hi Tanay,

    Placing the bulk capacitor closest to the source that is being decoupled is the overarching recommendation. So, my recommendation would be to place the 10uF capacitor closest to the larger number of vdd pins connected to the power plane. For example, somewhere inbetween pin 32 and 48 would suffice.

    Thanks,

    Lysny