TFP401A: The issue of the DE signal waveform

Xiang Hengwei

Part Number: TFP401A
Other Parts Discussed in Thread: TFP401

Hi ,

I probed the relation between DE and HSYNC . DE is high when data is vailable in active area. But sometime I find another high pluse DE signal ， in the same HSYNC Low pluse. The DE pluse width is about 260ns.

Is it normal for the chip? And have any resonable explanation? Waveform shown as follow. Thank you.

over 4 years ago

+1 Ikechukwu Anyiam over 4 years ago

TI__Mastermind 35130 points

Hi Xiang,

This is likely due to audio on the HDMI/DVI input. The TFP401 does not support audio in the HDMI/DVI stream as it messes up the encoding. Please check and ensure that your source is not embedding audio in the data stream.

Regards,

I.K.

0 Xiang Hengwei over 4 years ago in reply to Ikechukwu Anyiam

Prodigy 30 points

Hi I.K,

Your support is very appreciated.

I fix display resolution 1920X1080 @ 60Hz and enable audio on HDMI.

Because the timing between valid data and HSYNC is fixed, then just pick up the valid data by FPGA counter . Is there any potential issue?

Regards,

Xiang

+1 Ikechukwu Anyiam over 4 years ago in reply to Xiang Hengwei

TI__Mastermind 35130 points

Hi Xiang,

The TFP401 will not correctly decode a TMDS signal with embedded audio so I cannot guarantee any workarounds. But if you are observing the valid data being stable and are able to work with that with your FPGA then it should be fine.

Regards,

I.K.

Interface

Interface forum

TFP401A: The issue of the DE signal waveform