• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 32 subscribers
  • Views 198 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB913A-Q1: DS90UB925Q-Q1 instead of DS90UB913A-Q1?

Ray Vincent Aranzaso
Genius 15175 points
Part Number: DS90UB913A-Q1
Other Parts Discussed in Thread: DS90UB936-Q1, DS90UB925Q-Q1, DS90UR910-Q1

Hi,

Good Day. I have a customer who needs a converter IC which has to convert parallel 10 bit video data to MIPI-CSI2 interface.

I found a solution in E2E Forum Post and this is what I get: (Parallel 10 bit DVP -> DS90UB913A-Q1 -> DS90UB936-Q1 -> CSI-2)

This is the link where I get the solution: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/902762/parallel-data-to-mipi-csi-bridge

Since the PCLK frequency of the 2 devices are 25-100MHz, our customer needs 8MHz and he wants to ask if DS90UB925Q-Q1 can be a good alternative for DS90UB913A-Q1 for 8MHz?

I hope you can help us with his query. Thank you very much.

Best Regards,

Ray Vincent

  • 0
    TI__Mastermind 19480 points

    Hi Ray,

    The 925 is not compatible with the 936. The 925 is only compatible with the 926 and 928 deserializers, which do not offer conversion from parallel 10-bit video data to MIPI-CSI2 interface.

    The 936 is only compatible with the 935, 933, and 913A serializers. All of which support a PCLK of 25MHz to 100MHz.

    There are currently no FPD-Link solutions that meet both of your criteria (10-bit parallel to CSI-2 conversion and supports 8MHz PCLK). I recommend asking if the customer is able to increase the PCLK in their imager, to meet the minimum PCLK requirements of the 913A/936 pairing.

    Keep in mind that 10-bit mode operates at 50MHz to 100MHz PCLK frequency. And 12-bit LF mode operates at 25MHz to 50MHz. See datasheet for more details.

    You can also see the DS90UR905-Q1 and DS90UR910-Q1 devices for parallel to CSI-2 conversion. But they still don't meet your customer's PCLK requirement of 8MHz.

    Best,

    Justin Phan

  • 0 in reply to Justin Phan
    TI__Genius 15175 points

    Hi Justin,

    Good Day. Please see below the response of the customer to your suggestion. Thank you very much.

    Apart from the FPD solution, Is there any other solution available? Even if it is indirect solution, we can consider that. Still we are not able to find the solution for our application.

    Best Regards,

    Ray Vincent

  • 0 in reply to Ray Vincent Aranzaso
    TI__Mastermind 19480 points

    Hi Ray,

    I would recommend asking if the customer is able to configure the image sensor to have an increased pixel clock (PCLK). The PCLK is calculated using the following equation:

    PCLK = (Horizontal Active + Horizontal Blanking) x (Vertical Active + Vertical Blanking) x fps

    If your customer can configure the image sensor to increase the Horizontal or Vertical Blanking, then the PCLK can potentially meet the requirements of our existing products. If your image sensor is not able to be configured to increase Blanking, then an indirect and more costly solution would be to use something like an FPGA to add these Blanking periods to the data, before being fed into our FPD-Link products.

    Best,

    Justin Phan

  • 0 in reply to Justin Phan
    TI__Genius 15175 points

    Hi Justin,

    Good Day. Please see below the latest status of the query from the customer. Thank you very much.

    We have checked and unfortunately, the protocol is OVT-self defined, to guarantee the communication between OV6946 and OV426. Therefore OV426 is just to decode it and can't change the timing (hence pixel clock also).
    May i ask you that can we do multiply the PCLK by external IC? definitely, sampling will be also multiplied. But we can revert back to actual PCLK after Deserializer and accomplish the MIPI CSI 2 requirement?

    If clock multiplier is not good to go, then we have to find suitable FPGA solution that will be after Deserializer and should convert from parallel to MIPI CSI 2 interface. What is your suggestion on that? if it is well, we have to use parallel SerDes Solution.

    Best Regards,

    Ray Vincent

  • 0 in reply to Ray Vincent Aranzaso
    TI__Mastermind 19480 points

    Hi Ray,

    This is a bit outside of the scope that I can answer definitively, since it is not directly related to the configuration of our FPD-Link products. Our devices can transfer the video data at high speeds over a cable link and then reconstruct the same data and clock at the destination. However, our devices can't modify different parameters of the video data. These need to be done externally.

    It should be possible for you to use a 913A/936 setup, by using an external IC before the 913A to multiply the PCLK. And then revert the PCLK after the deserializer. But I am not familiar with your particular setup, so I can't be certain. I can only say with certainty that you need to meet the PCLK requirements listed in the datasheet, in order to successfully transfer data from the 913A to the 936.

    For your FPGA solution, you can use one of our FPD-Link II parallel-interface to parallel-interface SER/DES pairings, to transfer the video data to your destination. And then use an FPGA to convert from parallel to CSI-2 interface. You can refer to the 925/926 SerDes datasheets for a 24-bit parallel solution that support between 5MHz - 85MHz. 

    Best,

    Justin Phan