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Hi,
We are develop a USB device and ULPI interface is used. We tested our RTL in FPGA and using ULPI PHY (TUSB1210).
But we found high-speed detection handshake is not successful. When USB device send TX CMD (84 54) and TX CMD (40 00) to ULPI PHY to let it to send Chirp K,
then, USB device waits for Chirp K/J/K/J/K/J from usb host, but there is no Chirp K/J/K/J/K/J received.
The internal signal is shown as following figure(TX CMD (84 54) and TX CMD (40 00) are send to TUSB1210):
And we tested the signal of D+/D- after plugging USB cable to TSUB1210. It shows that signals keep toggling and this toggling is driven by TUSB1210.
The signals of D+/D- is shown in following figures:
From above, the amplitude of D- is larger than D+, this is a kind of strange.
So, do you have any suggestion for above testing result? I am looking forward to you reply.
Thanks and Best Regards,
Long
Hi Long:
What FPGA is used ? Can you send Schematic for review first?
Regards,
Brian
Hi Brian,
FPGA is XILINX VCU118.
Schematics is as following:
Please help to review and comment.
Could you also offer your e-mail?
Thanks!
Long
Long:
Is this deive?
Since you are using CLOCK as refclock, do you set clock mode to internal clock mode?
CPen is grounded in your schmatic, So Vbus switch will be off and there is no power on Vbat.
Regards,
Brian
Hi Brian,
Yes, it is device.
I connect REFCLOCK to GND to set clock mode to internal clock mode. Is there any other setting needed?
Because it is device mode, I don't think CPEN connecting to GND is an issue.
As mentioned above, We also tried to supply VBAT by external 5V and 3V3. Still, it failed.
Thanks!
Long
Long:
If DP pull-up (~1.5k) never seen by USB2 Host, HS chirp will never be sent by USB2 Host, Can you check?
Regards,
Brian
Hi Brain,
Sorry the delay to reply you. We just found out the root cause and solved it yesterday. It is not a circuit issue. Thanks for your support!
Best Regards,
Long