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TMDS181: output is unstable with 1080p, 59.94fps

Part Number: TMDS181

Hi Expert,

My customer have similar issue with the following E2E session

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/956055/tmds181rgzevm-using-eyescan-tool-it-is-not-stable-with-1080p-59-94-while-it-s-stable-with-1080p-60/3535748?tisearch=e2e-sitesearch&keymatch=TMDS181%25252525201080p#3535748

The output is unstable. The screen is flickering in every several second.

Customer try to check with below conditions,

480p : OK

720p : OK

1080p : NG

4K30p : OK

They found the issue with 1080p condition only.

Do you have any idea for the reason of this issue? why did this issue occur 1080p, 59.94fps only?

Thanks

Muk

  • Muk-san

    Can you measure the output clock frequency? 

    Are you in pin-strap or I2C mode? Is it possible to change DEV_FUNC_MODE to 0x00 (Redriver mode: 250 Mbps – 3.4 Gbps) and see if 1080p will work?

    Thanks

    David

  • Hello,

    It seems that the reduction of DEV_FUNC_MODE setting in Redriver mode of 00 has been improved.

    However, both "LANE_POLARITY" and "LANE_SWAP" are used in SWAP.
    The SWAP of LANE_POLARITY says Retimer mode only, but is it okay to use it in Redriver mode with SWAP?

  • When I checked it carefully, Positive and Negative were reversed in Redriver mode.
    At first glance, it seemed to be fine when connected directly to the HDMI analyzer, but the polarity reversal does not appear correctly in our set.

  • Hi,

    Polarity swap is only supported in the retimer mode, it is not supported in redriver mode. 

    Lane swap is supported in both the redriver and the retimer mode.

    Thanks

    David

  • That doesn't solve the problem of flickering at the original 1080p 59.94fps.
    Please give me advice.

  • Hi,

    Do you mean switching to the TMDS181 redriver mode does not solve the flicking issue? 

    What is the output clock frequency for both the redriver and the retimer mode? 

    Does the issue happen with one particular monitor? Does the issue get resolve when switching to 1080p at 60Hz?

    Thanks

    David 

  • I can't try Redriver mode.
    The reason is that the wiring is such that the board cannot be used without SWAP for both polarity and Lane.
    The output clock frequency is 148.3515MHz.
    This flick noise occurs on any monitor.
    When analyzed with an HDMI analyzer, the Hsync and Vsync signals are disturbed about once every 10 seconds.

  • Hi,

    The TMDS181 is outputting the correct clock frequency for this particular resolution. 

    Can the source support 1080 at 60Hz and does the monitor work? 

    Any chance you can measure the HSYNC and VSYNC frequency?

    Thanks

    David

  • Source does not support 60fps at 1080p resolution and only supports 59.94fps.
    There is nothing wrong with connecting Source and Sink directly, but sync is disturbed via TMDS181, so I think this is a problem with TMDS181.

  • Hi,

    Do you have I2C access to TMDS181? If you do, can you please dump out the TMDS181 Page 0 and Page 1 register? 

    The Page 0 register is in the TMDS181 datasheet.

    To access Page 1 register, please write 0x01 to register 0xFF first, and then dump out from register 0x00 to 0xB1. 

    This resolution was tested in the lab with TMDS181 and we verified it works with the TMDS181.

    Thanks

    David

  • Hello,
    The register dump value when flicker noise occurs at 1080p 59.94fps is as follows.

    Page 0
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 54 4d 44 53 31 38 31 20 01 c2 b3 18 00 00 00 0f    TMDS181 ????...?
    10: 00 00 00 00 00 80 00 70 00 00 00 00 00 00 00 00    .....?.p........
    20: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............

    Page 1
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: c3 01 3f 00 a0 00 00 00 02 00 00 33 00 00 13 00    ???.?...?..3..?.
    10: 0f 70 00 07 00 00 00 00 00 00 00 00 00 00 00 00    ?p.?............
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    30: 0e 70 01 00 00 00 00 00 08 00 00 08 04 06 00 00    ?p?.....?..???..
    40: 80 80 80 80 47 00 00 00 ff 01 e0 f0 03 20 47 34    ????G....???? G4
    50: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40    ............@@@@
    60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00    . ..............
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 5e 88 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ^?..............
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01    ...............?

  • Hi,

    I noticed you are setting 0x18 to register 0x0B, this will set the TX_TERM to 0x11 (75 to 150ohm). TX_TERM of 0x11 is for HDMI2.0. For 1080 resolution, can you please set it to 0x01?

    In your previous response, the Hsync and Vsync signals are disturbed about once every 10 seconds, can you please clarify this? Does this show up when connecting directly between the source and the sink?

    Thanks

    David 

  • The data sheet states the following:

    Transmit termination control
    TX_TERM_CTL = H, no transmit termination
    TX_TERM_CTL = L, transmit termination impedance in approximately 75 to 150 Ω
    TX_TERM_CTL = No Connect, automatically selects the termination impedance
    Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination
    2 Gbps > DR < 3.4 Gbps – 150

    With HDMI1.4 standard,
    1080p is 148.5MHz x 8bit =3.564Gbps
    4K30p is 297MHz x 8bit = 7.128Gbps

    So I thought TX_TERM was 0x11.
    I'll try it at 0x01 next week.

    And it is not confirmed that the Hsync signal and Vsync signal are disturbed when the source and sink are directly connected.

  • Hi,

    8 bit is the color depth, total bits/pixel is 3 * 8 = 24 bits

    So the total bandwidth = 297MHz * 24 * 10/8 = 8.91bps. 

    But this is the total bandwidth, each lane = 8.91/3 = 2.97Gbps -> 150 - 300ohm termination.

    Thanks

    David

  • At 1080p, 1.485Gbps <2Gbps, so the termination is not 0x01, isn't it 0x00?

    I tried 0x00 and 0x01 at 1080p, but both had sync disturbances.
    I also dumped the register.

    0x0B 0x08
    Page 0
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 54 4d 44 53 31 38 31 20 01 c2 93 08 61 00 00 0f    TMDS181 ????a..?
    10: 00 00 00 00 00 80 00 70 00 00 00 00 00 00 00 00    .....?.p........
    20: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............

    Page 1
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: c3 01 3f 00 a0 00 00 00 02 00 00 33 00 00 13 00    ???.?...?..3..?.
    10: 0f 50 00 07 01 00 00 00 00 00 00 00 00 00 00 00    ?P.??...........
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    30: 0e 70 01 00 00 00 00 00 08 00 00 08 04 06 00 00    ?p?.....?..???..
    40: 80 80 80 80 57 00 00 00 ff 01 f8 80 01 20 07 00    ????W....???? ?.
    50: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40    ............@@@@
    60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00    . ..............
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 5e 88 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ^?..............
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01    ...............?

    0x0B 0x00
    Page 0
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 54 4d 44 53 31 38 31 20 01 c2 93 00 61 00 00 0f    TMDS181 ???.a..?
    10: 00 00 00 00 00 80 00 70 00 00 02 00 00 00 00 00    .....?.p..?.....
    20: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............

    Page 1
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: c3 01 3f 00 a0 00 00 00 02 00 00 33 00 00 13 00    ???.?...?..3..?.
    10: 0f 40 00 07 01 00 00 00 00 00 00 00 00 00 00 00    ?@.??...........
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    30: 0e 70 01 00 00 00 00 00 08 00 00 08 04 06 00 00    ?p?.....?..???..
    40: 80 80 80 80 a3 00 00 00 ff 07 f0 01 01 20 07 00    ?????....???? ?.
    50: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40    ............@@@@
    60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00    . ..............
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 5e 88 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ^?..............
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01    ...............?

  • Hi,

    I would still enable adaptive EQ in register 0x0B (0xC3). But looking at both register dumps, I honestly do not see any issue. Both dumps show the TMDS181 is in retimer mode (Page 1, Register 0x00 -> 0xC3). The TMDS181 detects the input clock (Page 1, Register 0xB1 bit 7 -> 1). The input clock frequency is correct (Page 1, Register 0xB0 -> 0x5E, 5x25+25 = 150MHz). 

    The HSYNC and VSYNC is embedded in the TMDS data, the TMDS181 does not impact HSYNC and VSYNC, so I don't see how the TMDS181 can cause SYNC disturbance. Do you have a scope measurement of HSYNC and VSYNC?

    Thanks

    David  

  • Adaptive EQ has a register address of 0x0A as 0xB3, isn't it?
    I also tried this, but the sync is disturbed.

    Is it a TMDS oscilloscope waveform?
    Or is it a video of the HDMI analyzer screen that shows the disorder of sync?
    Which is better?

  • Hi,

    Adaptive EQ has a register address of 0x0A as 0xB3, isn't it?

    Correct, but the latest dump shows register 0x0A to be 0x93, not 0xB3.

    I am looking for the video of the HDMI analyzer screen that shows the disorder of sync. 

    Quick question, does the source have the audio enabled besides the video? If yes, is it possible to disable the audio?

    Thanks

    David

  • I tried various values for 0x0A, but the result was NG.
    Please wait for a video of the HDMI analyzer screen.
    If I can get the video, I will share it by email with TI Japan.

    Audio is currently enabled, but you can change it to DVI.
    Sync disturbance also occurs in DVI mode.

    By the way, which is the correct answer for 1080p TX_TERM, 0x00 or 0x01?

  • Hi,

    For 1080p, the bandwidth is 1.49G, so the TX_TERM is 0x00.

    Thanks

    David

  • Hi David,

    I sent e-mail to share the video.

    Update,

    They found the difference by jitter as below,

    Jitter 0.20Tbit 1080p source : flickering issue (NG)

    Jitter 0.12Tbit 1080p source : no problem (OK)

    Do you have any advice from this difference?

    The HDMI standard have 0.3Tbit Jitter test. please let me know the device ability of acceptable jitter max. (datasheet spec :0.3Tbit)

    Muk

  • Muk-san

    Please see my direct email response.

    Thanks

    David