TL16C2552: The control way of MF pin

Shinichi-san,

An engineer has been notified of your post and will respond by Monday. Thank you for your patience.

Regards,

Eric Hackett 

Hi Eric,

Thank you for your reply.

I'm looking forward to waiting the answer.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi Shinichi-san,

Shinichi Inoue said:

① When using the MF pin as OP by AFR,
When INT-Enable is enabled by the 3rd bit of the MCR register, it seems that the MF pin is forced to go low.
Is this recognition correct?

Yes that is correct: "When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to
a logic 1 (see MCR bit 3)." So Bit 3 of the MCR register controls the state of the buffer for the INT signal and OP output. When this bit is low the INT pin is high impeadance and OP is high. When this bit is high INT is enabled and OP is low. The OP signal can then be seen on the MF pin. This is what makes the MF go low.

Shinichi Inoue said:

② If the recognition of ① is correct
Is there a way to control the MF pin out of sync with the INT-Enable enable / disable setting?

The INT A and B is only enabled and disabled through the MCR register. You can however, separately disable the INT sources. This can be found in the IER register. However this wouldn't change the fact that the MF pin when OP is selected can only be toggled with bit 3 of the MCR register.

The MF pin however can serve as 3 funtions, OP, BAUDOUT, and RXRDY. So it may be possible to enable the INT and then control the MF pin through the RXRDY function. The RXRDY is controlled through the FCR register. You would have to toggle bit 3, this would however change the TXRDY and RXRDY levels at the same time. If you don't care about changing TXRDY when you change RXRDY this may be a viable solution.

I don't have access to a lab currently so I can't test this myself. However, this would be fairly easy for your customer to test by just enabling the INT feature and toggling the FCR bit to see what happens.

Best,

Chris

Hi Chris,

Thank you for your reply.

I'll share your suggestion with the customer .

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi Eric,

I shared your suggestion with the customer.

They have an additional question regarding PC16552.

Could you please advise.

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Currently, PC16552 is used. The FCR register is set to 0x87 and used.

Even if the setting value of bit 3 of the FCR register is switched from 0 to 1, the High / Low of RXRDY cannot be controlled arbitrary.

In addition, the RXRDY output (High / Low) is switched by the set trigger level and the arrival timing of the received data.

Is this recognition correct?

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I appreciate your great help and cooperation.

Best regards,

Shinichi

Shinichi-san,

Thanks for your patience on this, we're looking into it and will reply back shortly.

Regards,

Eric Hackett

Shinichi-san,

The customer is correct I misread the function of the FCR bit 3. The RXRDY is controlled by the bytes of data being received.

However, if the goal of the MF pin is to use it as transmission permitted state, using it as an RXRDY pin might work. While the device is receiving data the MF pin would be high. Then when it receives enough bytes, past the trigger level, the RXRDY pin will go low. This can be used for the functionality of knowing when your device is allowed to transmit data.

In order to change the function of the MF pin from it's default state you have to configure the AFR register. When the MF pin is in the RXRDY functionality it can operate separately from the INT enable and disable.

This is the best you can do with this device. Otherwise you may have to use a different pin or a different transceiver completely. There is no way to control the MF pin outside of the OP functionality.

Best,

Chris

Hi Chris,

Thank you for your reply.

I'll share your suggestion with the customer.

If they have an additional question, I consult you again.

I appreciate your great help and cooperation.

Best regards,

Shinichi