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SN65DSI86: Technical issues

Zhonghui Xu
Expert 5445 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi team,

I got a question from customer.

We use bridge chip sn65dsi86 to convert Mipi signal into EDP signal, and want to drive the screen directly. But there are only HDMI, DP, type C interfaces on the screen. Can we connect the EDP signal directly to the DP connector, and then connect the screen directly through the DP cable to drive the screen?

Thank you very much for your help.

Best regards,

  • 0
    TI__Guru**** 177396 points

    Hi,

    Yes, the DSI86 does support DP.

    Please note most DP screen does not support ASSR while DSI86 supports ASSR by default. To disable DSI86 ASSR support,  the first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:

    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 5445 points

    Hi Liu,

    Thank you for your reply.

    The external interface of the screen we use is DP, but the internal interface is EDP, and the LCD module is EDP. It's just that the interface left to the user after the screen is encapsulated is DP, tpye C or HDMI. Do you need to disable ASSR support of dsi86 in this case?

    Best regards

  • 0 in reply to Zhonghui Xu
    TI__Guru**** 177396 points

    Hi,

    Please check with the LCD module vendor to see if the LCF module supports ASSR. 

    I would have the pullup and pulldown option implemented on the TEST2 pin so I can enable/disable DSI86 ASSR as needed.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 5445 points

    Hi Liu,

    Thank you for your time.

    On the datasheet of dsi86, it is written "suitable for 60fps 4K 4096" × 2304 resolution (18bpp color), and 60fps WUXGA 1920 × 1200 resolution and 3D graphics display (120fps equivalent) "

    Is it because of the speed limitation of DSI interface that 18bpp is supported in 4K, 60fps, 4096x2304 resolution? If my resolution is 4000 * 2222, can the 60fps screen support 24bpp color?Or can 60fps only support 18bpp at 4K resolution?

    Best regards

  • 0 in reply to Zhonghui Xu
    TI__Guru**** 177396 points

    Hi,

    Correct, the supported resolution is limited by the 1.5Gbps per lane and 750MHz max DSI clock on the DSI side.

    You can use the following formula to verify if the particular resolution can be supported.

    Stream Bit Rate = PixelClock × bpp

    Max DSI Clock = Stream Bit Rate / (Number of DSI lane x 2)

    DSI Data Rate = 2 x Max DSI Clock

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 5445 points

    Hi Liu,

    Thank you for your reply.

    When using dsi86 dual channel configuration, do you need to strictly control the data synchronization of two channels. Can there be phase difference allowed?

    For example, we configure channel A to receive odd pixel data, channel B receives even pixel point data. For the same frame image, we need to meet the requirements of pixel points 1, 3, 5... And pixel points 2, 4, 6... Simultaneously appearing in A and B channels, or can we accept a certain phase delay. The data of two channels can be synchronized within the chip. If phase delay is allowed, how much phase delay can it be?

    Best regards

  • 0 in reply to Zhonghui Xu
    TI__Guru**** 177396 points

    Hi,

    For dual DSI channels, the DSI86 will use VSS, VSE, and HSS packets from channel A.

    The DSI86 will use channel A events to recreate the same timings on the DisplayPort interface. The VSS, VSE, and HSS packets from channel B are used to internally align data on channel B to channel A.

    Thanks

    David