• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 169 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FPD-Link Measurement Checklist

Jared Becker
Genius 11515 points

Hi Team,

I am looking to align with the FPD-Link team on a checklist that customers should follow when the implement an FPD-Link device. Below is the list I have thought through. Please let me know if there is anything to add or change.

  • Power Up Sequence
    • Check to ensure the power sequence matches the datasheet recommendation
  • Power Rail Voltage Levels
    • Check to ensure the voltage levels are within the datasheet specification
  • FPD-Link Eye Diagram
    • Check to ensure the eye opening and jitter is within the datasheet specification
  • Interface Protocol Measurement
    • Check to ensure the interface between the SoC and FPD-Link device is within spec for the given protocol

Thank you,

Jared

  • 0
    TI__Guru* 98535 points

    Hello Jared,

    Eye diagram measurement is not something we typically recommend there is a need to do as part of the system qualification since we do not have pass/fail specifications for that. 

    I agree with the rest of your list and would add on the following:

    • Power Up Sequence
      • Check to ensure the power sequence matches the datasheet recommendation
    • Power Rail Voltage Levels
      • Check to ensure the voltage levels are within the datasheet specification
    • Power Rail Noise
      • Check to ensure noise at the pins of the device power inputs meet the p-p noise specifications in the datasheet 
    • Parallel interface clock/data verification 
      • Check to ensure the PCLK/CLKIN input to the serializer meets the device's jitter and frequency specifications 
      • Check to ensure that the clock to data skew or setup and hold time of the parallel interface meets the serializer datasheet specification where applicable 
    • Channel verification 
      • Ensure that the PCB on each side (SER/DES) frequency domain characteristics meet the PCB IL/RL budget from the corresponding channel spec for the device pair  
      • Ensure that the cable between SER/DES frequency domain characteristics meet the cable IL/RL budget from the corresponding channel spec for the device pair  
      • Ensure that the total channel between SER/DES frequency domain characteristics meet the total channel budget from the corresponding channel spec for the device pair  

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Genius 11515 points

    Hi Casey,

    Thanks for the review. When a customer is using DP or DSI, what should they be evaluating in terms of clocking/jitter?

    -Jared

  • +1 in reply to Jared Becker
    TI__Guru* 98535 points

    Hello Jared,

    For DSI, they should qualify their DSI source against the official MIPI DPHY CTS which can be retrieved directly from MIPI, and particularly in PCLK from DSI reference clock mode for 941AS, they should qualify that the DSI input clock jitter is meeting the tDSI_JIT parameter in the 941AS datasheet (since the DSI clock is used to directly source the FPD3 PLL). 

    For DP, they should follow the DP v1.4 CTS to qualify the DP source parameters. 

    Basically both the DSI interfaces and DP interfaces are industry standard interfaces which we have qualified the devices to. There is a receiver CTS which we qualify our devices to meet, and then the transmitter CTS is what the customer would qualify their source to meet. The only small exception where we specify something outside the standard is the DSI jitter for 941AS when working in the DSI reference clock mode. If working in the other modes such as external REFCLK mode, then you really only need to qualify against the DSI transmit CTS since the DSI input jitter doesn't affect the FPD3 output jitter. For 98x the input jitter does not affect output jitter at all since the FPD side is clocked from the mandatory 27MHz REFCLK  

    Best Regards,

    Casey