DP83822I: Timing Requirements, RMII Transmit Timing

Deepeshwar Kumar

Part Number: DP83822I

Hi TI,

I need more info regarding the timing constraints given for the RMII Transmit Timing in the datasheet.
1. What is the maximum setup time value for "TX_D[1:0] and TX_EN Data Setup to XI rising"?
2. What is the maximum hold time value for "TX_D[1:0] and TX_EN Data Hold from XI rising"?

What value we need to consider for them, can you please clarify this missing information? We need this information to add in timing constraints for FPGA. I have attached a timing information image for reference.

Regards,

Deepeshwar

over 4 years ago

0 Vikram Sharma over 4 years ago

TI__Genius 16030 points

Hello Deepeshwar,

Minimum value of requried setup and hold time should be sufficient for your timing constraint. You may drive the maximum of these by subtracting the other spec from the time period of XI (8ns).

Regards,

Vikram

0 Deepeshwar Kumar over 4 years ago in reply to Vikram Sharma

Prodigy 40 points

Hi Vikram,

Can I calculate setup max and Hold Max requirements by following equation:

For Setup Max = Clock period - Setup min - CLK_O/P_Delay

For Hold Max = Clock period - setup min

Please confirm.

Regards,

Deepeshwar

0 Vikram Sharma over 4 years ago in reply to Deepeshwar Kumar

TI__Genius 16030 points

What is clk_o/p_delay?

Regards,

Vikram

0 Deepeshwar Kumar over 4 years ago in reply to Vikram Sharma

Prodigy 40 points

Hi Vikram,

clk_o/p_delay is Clock to Output delay at source of signal. Basically Data valid after launch flop clock edge.

I am correcting myself for max Hold time:

Max Hold time = Clock Period/2 + Clock to Output delay

Please review my equations and get back.

Regards,

Deepeshwar

0 Vikram Sharma over 4 years ago in reply to Deepeshwar Kumar

TI__Genius 16030 points

Hello Deepeshwar,

Unfortunately we are not familiar with how exactly you should specifiy timing constaints on the FPGA, how clk_o/p_delay comes into picture and will not be able to specify the exact constraints required for FPGA programming, but ultimately at PHY's TX "pins" you need to make sure that :

1. Min hold time is met

2. Min hold time is met

3. Take this into consideration : XI clock period is 50MHz and data toggle only with respect to positive edge of clock

Regards,

Vikram

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DP83822I: Timing Requirements, RMII Transmit Timing