DP83867IR: 1000BASE-T Auto-Negotiation Next Page Implementation

Hello Yoshihito-san,

If you configure the PHY in the desired mode "1000BASE-T , Master / Slave auto mode" you dont need to read/write any extra register for PHY to link-up. Are you configuring the PHY using strap resistors?

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Regards,

Vikram

Vikram-san,

Thank you for your confirmation and reply.

"you dont need to read / write any extra register for PHY to link-up"

⇒ "1000BASE-T, Master / Slave auto mode"
To the composition of
Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0007
Is it unnecessary?
I knew that nextpage was essential for implementing 1000BASE-T.
If nextpage is not needed and Auto-Negotiation 1000BASE-T can be implemented, when should nextpage be used?

"Are you configuring the PHY using strap resistors?"

⇒ Is it the content of pages 50 to 51 of the data sheet?
I was not aware of the contents described here.
Does it mean that link-up is possible only by setting the resistance?

Regards,

takahashi

Vikram-san

Thank you for your reply.
Related to the strap resistance you taught,
Configuration Register 1 (CFG1), Address 0x0009
I succeeded in linking up by changing bit 9 of.

Looking at the IEEE802.3ab standard, nextpage is required for link-up, but this time, the nextpage register is not used.
Why did you succeed in linking up?

Regards,

takahashi

Hello San,

I am not sure whether I got your question or why you are saying that nextpage register is not used. 867 is compliant with IEEE standard and may be you can go through section: 8.4.3.4 and 8.4.3.5 of datasheet to get more clarity.

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Regards,

Vikram

Vikram-san

What I don't understand is:

・Looking at the IEEE802.3ab standard, it is stated that next page needs to be added in order to enable 1000BASE-T auto-negotiation.
・However, in DP83867IR, without adding nextpage register You can enable 1000BASE-T auto-negotiation.
・Does the DP83867IR have the settings required for 1000BASE-T auto-negotiation as a function, and the user does not need to set them?

Regards,

takahashi

Hello San,

Kindly share the content of registers 0x0004, 0x0005, 0x0006, 0x0007, 0x0008 and 0x0009 after your succesful link-up in 1G mode in the system under test.

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Regards,

Vikram

Hello Vikram san

1000BASE-T Auto-negotiation We will inform you about the register settings at the time of link-up.

・ Enable RGMII mode
-Link-up is completed, but only "1101" is output from RX_D [0 ... 3].

Basic Mode Control Register (BMCR), Address 0x0000 

reg0_set(15) <= '0'; --RESET
reg0_set(14) <= '0'; --LOOPBACK
reg0_set(13) <= '0'; --SPEED SELECTION LSB
reg0_set(12) <= '1'; --AUTO-NEGOTIATION ENABLE
reg0_set(11) <= '0'; --POWER DOWN
reg0_set(10) <= '0'; --ISOLATE
reg0_set( 9) <= '0'; --RESTART AUTO-NEGOTIATION
reg0_set( 8) <= '1'; --DUPLEX MODE
reg0_set( 7) <= '0'; --COLLISION TEST
reg0_set( 6) <= '1'; --SPEED SELECTION MSB
reg0_set( 5) <= '0'; --↓RESERVED
reg0_set( 4) <= '0';
reg0_set( 3) <= '0';
reg0_set( 2) <= '0';
reg0_set( 1) <= '0';
reg0_set( 0) <= '0';

Auto-Negotiation Advertisement Register (ANAR), Address 0x0004

reg4_set(15) <= '0'; --NP
reg4_set(14) <= '0'; --RESERVED
reg4_set(13) <= '0'; --RF
reg4_set(12) <= '0'; --RESERVED
reg4_set(11) <= '0'; --ASM_DIR
reg4_set(10) <= '0'; --PAUSE
reg4_set( 9) <= '0'; --T4
reg4_set( 8) <= '0'; --TX_FD
reg4_set( 7) <= '0'; --TX
reg4_set( 6) <= '0'; --10_FD
reg4_set( 5) <= '0'; --10BASETe_EN
reg4_set( 4) <= '0'; --↓SELECTOR
reg4_set( 3) <= '0';
reg4_set( 2) <= '0';
reg4_set( 1) <= '0';
reg4_set( 0) <= '1';

Configuration Register 1 (CFG1), Address 0x0009

reg9_set(15) <= '0'; --↓TEST MODE
reg9_set(14) <= '0';
reg9_set(13) <= '0';
reg9_set(12) <= '0'; --MASTER / SLAVE MANUAL CONFIGURATION
reg9_set(11) <= '0'; --MASTER / SLAVE CONFIGURATION VALUE
reg9_set(10) <= '0'; --PORT TYPE
reg9_set( 9) <= '1'; --1000BASE-T FULL DUPLEX
reg9_set( 8) <= '0'; --1000BASE-T HALF DUPLEX
reg9_set( 7) <= '0'; --TDR AUTO RUN
reg9_set( 6) <= '0'; --↓RESERVED
reg9_set( 5) <= '0';
reg9_set( 4) <= '0';
reg9_set( 3) <= '0';
reg9_set( 2) <= '0';
reg9_set( 1) <= '0';
reg9_set( 0) <= '0';

Register Control Register (REGCR), Address 0x000D

reg13_0_set(15) <= '0'; --↓Function
reg13_0_set(14) <= '0';
reg13_0_set(13) <= '0'; --↓RESERVED
reg13_0_set(12) <= '0';
reg13_0_set(11) <= '0';
reg13_0_set(10) <= '0';
reg13_0_set( 9) <= '0';
reg13_0_set( 8) <= '0';
reg13_0_set( 7) <= '0';
reg13_0_set( 6) <= '0';
reg13_0_set( 5) <= '0';
reg13_0_set( 4) <= '1'; --↓DEVAD
reg13_0_set( 3) <= '1';
reg13_0_set( 2) <= '1';
reg13_0_set( 1) <= '1';
reg13_0_set( 0) <= '1';

Address or Data Register (ADDAR) address 0x000E

reg14_0_set(15) <= '0'; --↓Address / Data
reg14_0_set(14) <= '0';
reg14_0_set(13) <= '0';
reg14_0_set(12) <= '0';
reg14_0_set(11) <= '0';
reg14_0_set(10) <= '0';
reg14_0_set( 9) <= '0';
reg14_0_set( 8) <= '0';
reg14_0_set( 7) <= '0';
reg14_0_set( 6) <= '0';
reg14_0_set( 5) <= '1';
reg14_0_set( 4) <= '1';
reg14_0_set( 3) <= '0';
reg14_0_set( 2) <= '0';
reg14_0_set( 1) <= '1';
reg14_0_set( 0) <= '0';

Register Control Register (REGCR), Address 0x000D

reg13_1_set(15) <= '1'; --↓Function
reg13_1_set(14) <= '0';
reg13_1_set(13) <= '0'; --↓RESERVED
reg13_1_set(12) <= '0';
reg13_1_set(11) <= '0';
reg13_1_set(10) <= '0';
reg13_1_set( 9) <= '0';
reg13_1_set( 8) <= '0';
reg13_1_set( 7) <= '0';
reg13_1_set( 6) <= '0';
reg13_1_set( 5) <= '0';
reg13_1_set( 4) <= '1'; --↓DEVAD
reg13_1_set( 3) <= '1';
reg13_1_set( 2) <= '1';
reg13_1_set( 1) <= '1';
reg13_1_set( 0) <= '1';

Address or Data Register (ADDAR) address 0x000E

reg14_1_set(15) <= '0'; --↓Address / Data ↓RESERVED
reg14_1_set(14) <= '0';
reg14_1_set(13) <= '0';
reg14_1_set(12) <= '0';
reg14_1_set(11) <= '0';
reg14_1_set(10) <= '0';
reg14_1_set( 9) <= '0';
reg14_1_set( 8) <= '0';
reg14_1_set( 7) <= '1'; -- RGMII_EN
reg14_1_set( 6) <= '1'; -- ↓RGMII_RX_HALF_FULL_THR
reg14_1_set( 5) <= '0';
reg14_1_set( 4) <= '1'; -- ↓RGMII_TX_HALF_FULL_THR
reg14_1_set( 3) <= '0';
reg14_1_set( 2) <= '0'; -- RESERVED
reg14_1_set( 1) <= '0'; -- RGMII_TX_CLK_DELAY
reg14_1_set( 0) <= '0'; -- RGMII_RX_CLK_DELAY

PHY Control Register (PHYCR), Address 0x0010

reg16_set(15) <= '0'; -- TX FIFO Depth
reg16_set(14) <= '0'; -- TX FIFO Depth
reg16_set(13) <= '0'; -- ↓RESERVED
reg16_set(12) <= '0';
reg16_set(11) <= '0';
reg16_set(10) <= '0'; -- FORCE_LINK_GOOD
reg16_set( 9) <= '0'; -- POWER_SAVE_MODE
reg16_set( 8) <= '0'; -- POWER_SAVE_MODE
reg16_set( 7) <= '0'; -- DEEP_POWER_DOWN_EN
reg16_set( 6) <= '1'; -- MDI_CROSSOVER
reg16_set( 5) <= '0'; -- MDI_CROSSOVER
reg16_set( 4) <= '0'; -- DISABLE_CLK_125
reg16_set( 3) <= '0'; -- RESERVED
reg16_set( 2) <= '0'; -- STANDBY_MODE
reg16_set( 1) <= '0'; -- LINE_DRIVER_INV_EN
reg16_set( 0) <= '0'; -- DISABLE_JABBER

 Is there a problem with the register settings? 

Hello San,

I think I did not understand your last reply. Do you mean to say that you are not getting a link-up anymore? From our earlier discussion, I thought that your link is up and the main question is related to why link-up was successful without next page. Kindly help clarify.

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Regards,

Vikram

Hello Vikram san

I'm sorry I couldn't explain it well.

We know that the linkup is complete.
We have confirmed the 1000BASE-T link-up between the evaluation board and the connected PC or switching hub.

Originally I was asking why the linkup was completed with the attached register settings.
As mentioned above, we are not using the nextpage register.

Yesterday's question is different.
After the link-up is completed with the above register settings,

data is sent to the PHY IC, but it seems that only "1101" is output from RX_D [0 ... 3].

I think this is a different agenda, so I will ask a different theme in this forum.

I'm not in a hurry about why I completed the link-up, so please close it once.

Thank you for your polite response.

Thank you very much.

Regards,

takahashi

Sure Takahashi-san. You may open the new thread for better tracking/logging of the new query.