DS90UB948-Q1: Interface forum

Betty Guo

Part Number: DS90UB948-Q1

Hi team,

customer found when 948 VDD3.3V power up, the CLK have a pulse, see the below picture 1， The PDB is low.

search on E2E, I find some thread with the same issue that when 3.3V power on, 948 lock or GPIO have pulse, but didn't find the root cause and solution.

in additional, if 1.2V power on before 3.3V, the pulse can be reduce some, see the picture 2. but as 948 d/s, the 1.2V should not power before 3.3V.

so, we need your help is that how to reduce the pulse, at the same time meet 948 power sequence. what's your recommendation about delay time between 3.3V and 1.2V?

thank you.

over 4 years ago

0 Solomon Ali over 4 years ago

TI__Intellectual 1905 points

Hi Betty,

Thanks for reaching out.

Could you help answer the following questions:
1. What is the VDD33 rise time? Does it meet the requirement of >= 0.2ms?
2. If yes, does the customer observe this pulse on a single pin (LVDS CLK1) only? or is it observed on multiple other pins?
If the second option, what are these pins?

Best regards,
Solomon

0 Betty Guo over 4 years ago in reply to Solomon Ali

TI__Expert 7300 points

Hi Solomon,

1. yes, it meet the ，0.2ms requirement.

2. it observed on multiple pins, GPIO, CLK, LOCK DATA

0 Betty Guo over 4 years ago in reply to Solomon Ali

TI__Expert 7300 points

Hi Solomon,

you can search on E2E about 948 issue when 3.3V power on, there have some similar problems. for examples:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1001757/ds90ub948-q1-gpio-has-a-2v-plus-voltage-when-vdd33-power-up?tisearch=e2e-sitesearch&keymatch=DS90UB948-Q1%25252525252525203.3V%2525252525252520power%2525252525252520on#

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/964433/ds90ub948-q1-ds90ub948-q1-power-up-charateristic/3566222?tisearch=e2e-sitesearch&keymatch=DS90UB948-Q1%25203.3V%2520power%2520on#3566222

0 Solomon Ali over 4 years ago in reply to Betty Guo

TI__Intellectual 1905 points

Hi Betty,

I don't see VDDIO in the above screenshots. Could you check what the customer is using for VDDIO? 3.3V or 1.8V?
Also, could you ask the customer to share a screenshot of VDD33, VDDIO, and VDD12 with the datasheet recommended power sequence?

Regards,
Solomon

0 Betty Guo over 4 years ago in reply to Solomon Ali

TI__Expert 7300 points

Solomon,

the first waveform I provide in the first question is VDD33 VDD10 and VDD12 power sequence ! they are meet 948 datasheet and have pulse on CLK or other pins when 3.3V power on. VDDIO is use 3.3V , same with VDD3.3

I think it may be a general problems because I find other people ask this. please give some help suggestions, does it is normal for 948 when power on 3.3V

0 Solomon Ali over 4 years ago in reply to Betty Guo

TI__Intellectual 1905 points

Hi Betty,

Thanks for the confirmation.

Re: "
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/964433/ds90ub948-q1-ds90ub948-q1-power-up-charateristic/3566222?tisearch=e2e-sitesearch&keymatch=DS90UB948-Q1%25203.3V%2520power%2520on#3566222
"
In this E2E thread, it explains that it might be due to “leakage from the multi-rails power-on sequence”. Also, it explained “to reduce this pulse, you can reduce the time latency between different supply rails.”
So, to test if you observing the same issue, could you try to reduce the time between powering on different supply rails (VDD33, VDDIO, and VDD12 on at the same time, delta-t ~0s) and let us know if you see any improvement?

Best regards,
Solomon

0 Betty Guo over 4 years ago in reply to Solomon Ali

TI__Expert 7300 points

Solomon,

yes, reduce the delay time between VDD33 and VDD12 can improve. if the VDD12 power on before VDD33, the pulse can be reduce more, but it can meet datasheet requirement.

so your suggestions is that VDD33 and VDD12 power on at the same time? we are still confuse why there have leakage from the multi-rails power on sequence? can you explain more about it?

0 Solomon Ali over 4 years ago in reply to Betty Guo

TI__Intellectual 1905 points

Hi Betty,

Re: "so your suggestions is that VDD33 and VDD12 power on at the same time?"
Yes, and this still meets the datasheet requirement as shown below:

Re: "we are still confuse why there have leakage from the multi-rails power on sequence? can you explain more about it?"
As explained in the previous E2E thread, "the leakage current is different due to process variation but this is normal behavior for the silicon IC."

Best regards,
Solomon