SN65DSI84-Q1: Regarding the DSI DPHY lane clock requirement

Arun Gangadharan

Part Number: SN65DSI84-Q1

Hi Experts,

Can someone explain on the queries given below:

1. The data sheet section 8.3.1 says that DSI PHY Clock needs to be run in specific mode (HS free running/continuous) ? Can this be explained ? Is it High speed configuration of DPHY in SoC or any other specific mode ?

2. We dont have the REFCLK sourced externally, We are relying on DSI DPHY clock. Datasheet says that test pattern mode will ignore the DSI inputs. Does test pattern mode uses the DSI clock in this case ?

Thanks,

Arun Gangadharan

over 4 years ago

+1 David (ASIC) Liu over 4 years ago

TI__Guru**** 179636 points

Arun

1. The MIPI source needs to make sure to drive the clock in high speed state only, no low power state.

2. In test pattern mode the device does not use any input DSI data. It only uses the DSI CLK or optionally an external REFCLK. The clock is used to internally generate the pattern and output it to a display.

Thanks

David

0 Arun Gangadharan over 4 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Appreciated. Thank you David for the prompt reply.

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SN65DSI84-Q1: Regarding the DSI DPHY lane clock requirement