TUSB7320: will you tell me the spec of power up sequence of TUSB7320?

user6145698

Part Number: TUSB7320

will you tell me the spec of power up sequence of TUSB7320?

①timing spec between 1.1-V and 3.3-V power-up
②timing spec between supply voltage and CLK

If we violate the above timing spec,
what failure modes happens?
Is there data of failure rate when violating timing spec?

over 4 years ago

0 Brian Zhou over 4 years ago

TI__Guru*** 146515 points

Hi:

There is no sequence between 1.1v, 3.3v and CLK. but most important to keep GRST# low until 1.1v, 3.3v and CLK stable.

Also keep PERST low at least 100us after PCIe reference clk is stable. Pls check page 104 on datasheet.

Regards,

brian

0 user6145698 over 4 years ago in reply to Brian Zhou

Prodigy 40 points

Thank you for your answer.

Is it no problem if the sequence of (CLK →　power supply)?

I found your answer (https://e2e.ti.com/support/interface-group/interface/f/interface-forum/997234/tusb7320-noise-occurs-in-the-power-supply/3742301?tisearch=e2e-sitesearch&keymatch=TUSB7320#3742301)

The above answer said that you recommend　the OSC clock is input after VDD.

please tell me the detail?

0 Brian Zhou over 4 years ago in reply to user6145698

TI__Guru*** 146515 points

Hi:

CLK can start early than power supply , but no more than 100us. When power is off, Any stress on IO pin will backdrive the device and cause the leakage. If the backdrive is consistent and last long time, It may hurt device life time.

Regards,

Brian

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TUSB7320: will you tell me the spec of power up sequence of TUSB7320?