DS90UB941AS-Q1: The specifical requoremnet of DSI packet order in Asymmetric Splitting With DSI VC-IDs

The customer has asked two questions in the E2Echina forum, and this is the first question, and I think this is similar to the one above, so I write it Here they are. Because I am not familiar with SERDER, and I translated them into English as follows. Please indicate if there are any unclear descriptions.

The customer intends to implement 1 link DSI Split to 2 link to both screens using DS90UB941AS-Q1. In the 8.4.6.4.1.1 Symmetric Splicing – left/right section, is this the left/right image spliced into one row, and the left and right two rows packaged as one row for the 941AS? If the left and right rows are spliced into one row, how does the 941 recognize the left and right rows and then split the screen? ? 941 Working in this mode, what are the requirements for packets that send left and right rows of data?

Hi Amy,

You can look up the DSI packet order in the DSI specification in "8.11.2 Non-Burst Mode with Sync Pulses" and "8.11.3 Non-Burst Mode with Sync Events" and "8.11.4 Burst Mode".

Can you describe what the input and output video format they are trying to achieve?

Regards,

Michael W.

Hi Michael,

Thank you for your reply. Below is the customer's feedback:"

I know what you described.But what's the difference of packet order between  Asymmetric Splitting With DSI VC-IDs mode  and the specification described?  Is the difference  just the interlace of VC0 and VC1??

Input video mode :1080p 60fps RGB24

trying to achieve: 2 link 1080p rgb24 to LVDS DISPLAY "

Thanks,

Amy

Hi Amy,

The difference is just the interlaces VC0 and VC1.

If you are trying to send 2 1080p videos over one DSI port you might find that the video bandwidth is larger than the DSI can support.

What SOC are they using?

Regards,

Michael W.