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DP83869HM: Power sequence debugging

Part Number: DP83869HM

Hi Team,

I have a question about power sequence of DP83869HM.

My customer is evaluating DP83869HM and they faced below problem.

They are looking for the root cause and they have concern about power sequence.

[Problem]

DP83869HM doesn't establish the link with etherhub.

when read the register value, All register value are FFFF.

after HW reset, return to normal behavior(establish the link).

[Concern]

t1_VDDIO(supply ramp time) is close to 0.5ms_min.

below pink is VDDIO and supply ramp time is 1.08ms but depending on % of rise time(e.g. 20% - 80%), it might be less than 0.5ms. 

[Question]

when t1_VDDIO is less than 0.5ms_min, does Phy duplicate above problem?

If yes, are there any  sweet time that can easily duplicate above problem?

Regards,

Kai

  • Hi Kai,

    Can you confirm if RX_CLK and CLKOUT signals are present and at the correct frequency when there is a suspected POR issue?

    The PHY has been characterized according to datasheet parameters, so it's difficult to say if these issues can be reproduced. I don't want to recommend any configurations outside of the datasheet because we don't know the impact to the PHY, but you can try holding the PHY in reset until all supplies have fully ramped. This should allow the PHY to be powered on correctly.

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults”, and it is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • Hi Lucas,

    I attached RX_CLK and CLKOUT waveform.

    could you help how to investigate this root cause from attached excel file?

    DP83869HM_RXCLK_CLKOUT.xlsx

    Regards,

    Kai

  • Hi Kai,

    If CLKOUT and RX_CLK aren't present, this points to a POR issue.

    Is it possible to ramp all supplies at the same time? If not possible with your custom board, is it possible using the EVM which should require only a single 5V supply and has LDOs to step down the voltage for each PHY rail?

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Lucas,

    Customer followed correct power up sequence but why there is POR issue?

    customer is evaluating DP83869HM on their prototype so I will ask tomorrow but ramp all supplies at the same time should be impossible since it needs design change.

    regarding below your comment, I cannot clearly understand.

    Does the EVM mean DP83869HM EVM?

    Does below your comment imply that using external 5V supply and LDOs, we supply each DP83869HM EVM PHY rail?

    I don't think it can help to resolve customer issue. 

    "is it possible using the EVM which should require only a single 5V supply and has LDOs to step down the voltage for each PHY rail?"

    Regards,

    Kai

  • Hi Kai,

    Since we've taken this discussion offline, I'll be closing this thread.

    Thanks,

    Lucas