DP83867E: SGMII XILINX, working problem

Hi Krzysztof,

It looks like the only registers that have an issue being read are extended registers. Could you check to see if the correct method of accessing extended registers is being used? Refer to section 8.4.2.1 of the datasheet for more information.

Can you also include register 0x37 in your register dump? Note that this is also an extended register.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Thanks Lucas,

thanks to Your advice We get acess to extended registers. Meanwhile We changed phyaddress to 0x01 by removing strap resistors from d2 and d3 lines. In baremetal application we cannot go throught DHCP, but autonegotiation is completed and ping request is not working. Do You have any sugestions what could help? 

Also we tried to use u-boot, but with no effect. On RX_CTRL we dont have strap resistors, so when we read 0x0031 register we noticed that INT_TST_MODE_1 is "1", (reg 0x0031= 0x10B0) so we cleared this bit manually.

ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr -1, interface sgmii

Warning: ethernet@ff0e0000 (eth0) using random MAC address - 46:6c:75:b5:a5:23
eth0: ethernet@ff0e0000
Hit any key to stop autoboot: 0
ZynqMP> mii read 0x1 0x0
1140
ZynqMP> mii read 0x1 0x1
796D
ZynqMP> mii read 0x1 0x2
2000
ZynqMP> mii read 0x1 0x3
A231
ZynqMP> mii read 0x1 0x4
01E1
ZynqMP> mii read 0x1 0x5
C1E1
ZynqMP> mii read 0x1 0x6
006F
ZynqMP> mii read 0x1 0x7
2001
ZynqMP> mii read 0x1 0x8
48A7
ZynqMP> mii read 0x1 0x9
0300
ZynqMP> mii read 0x1 0xa
3C00
ZynqMP> mii read 0x1 0xb
0000
ZynqMP> mii read 0x1 0xc
0000
ZynqMP> mii read 0x1 0xd
401F
ZynqMP> mii read 0x1 0xe
0000
ZynqMP> mii read 0x1 0xf
3000
ZynqMP> mii read 0x1 0x10
5840
ZynqMP> mii read 0x1 0x11
BC02
ZynqMP> mii read 0x1 0x12
0000
ZynqMP> mii read 0x1 0x13
1C40
ZynqMP> mii read 0x1 0x14
29C7
ZynqMP> mii read 0x1 0x15
0000
ZynqMP> mii read 0x1 0x16
0000
ZynqMP> mii read 0x1 0x17
0040
ZynqMP> mii read 0x1 0x18
6150
ZynqMP> mii read 0x1 0x19
4444
ZynqMP> mii read 0x1 0x1a
0002
ZynqMP> mii read 0x1 0x1b
0000
ZynqMP> mii read 0x1 0x1c
0000
ZynqMP> mii read 0x1 0x1d
0000
ZynqMP> mii read 0x1 0x1e
0002
ZynqMP> mii read 0x1 0x1f
0000
ZynqMP> mii write 0x1 0xD 0x001F
ZynqMP> mii write 0x1 0xE 0x006E
ZynqMP> mii write 0x1 0xD 0x401F
ZynqMP> mii read 0x1 0xE
0801
ZynqMP> mii write 0x1 0xD 0x001F
ZynqMP> mii write 0x1 0xE 0x006F
ZynqMP> mii write 0x1 0xD 0x401F
ZynqMP> mii read 0x1 0xE
0000
ZynqMP> mii write 0x1 0xD 0x001F
ZynqMP> mii write 0x1 0xE 0x0037
ZynqMP> mii write 0x1 0xD 0x401F
ZynqMP> mii read 0x1 0xE
0000
ZynqMP> mii write 0x1 0xD 0x001F
ZynqMP> mii write 0x1 0xE 0x0031
ZynqMP> mii write 0x1 0xD 0x401F
ZynqMP> mii read 0x1 0xE
0060
ZynqMP>

Hi Krzysztof,

Based on register 0x37 value, it looks like auto-negotiation for sgmii has not completed. Can you check the DP83867 troubleshooting guide section 2.10 and follow the steps to see if you are able to establish an sgmii link?

https://www.ti.com/lit/an/snla246a/snla246a.pdf?ts=1624988638418&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83867E

You may need to adjust the sgmii auto-negotiation timer in register 0x31.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Thanks Lucas,

We checked this list, our hardware looks ok. Also we tried to change auto-negotiation timer in register 0x31 with no effect. Also we read this register:

ZynqMP> mii write 0x1 0xD 0x001F
ZynqMP> mii write 0x1 0xE 0x0135
ZynqMP> mii write 0x1 0xD 0x401F
ZynqMP> mii read 0x1 0xE
0000

Do You have any other sugestions?

Hi Krzysztof,

Could you provide a schematic for review?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

our schematic is above. We dont have strap on RX_CTRL pin, but we clear it manually by mii interface.

Clock for GTR bank is 125 MHz.

Thanks for any suggestions.

Also we have reversed polarity on TX line. We write to reg 0x01D5 : 0xF502 to change polarity in DP.

Hi Krzysztof,

We're taking a look at your schematic and will get back to you by Tuesday.

Thanks,

Lucas

Assuming, with good strap configutation and no polarity swap, DP83867 should work without any code modyfications.