Part Number: DS90UB962-Q1
Other Parts Discussed in Thread: DS90UB935-Q1
Expert,
I put I2C master at UB962 side to control camera at UB935 side. Both side run I2C in 400KHz with clock stretch but failed. (100KHz I2C operation is OK)
I 've read "I2C over DS90UB913/4 FPD-Link III with Bidirectional Control Channel" and "I2C Communication Over FPD-Link III with Bidirectional Control Channel".
I have some questions about DS90UB962-Q1 with DS90UB935-Q1 I2C speed calculation.
I2C mast is at DS90UB962-Q1 side. External Ref clk is 25MHz for 962. UB935 works at synchronize clock mode.
According to App notes, I2C throughput is 9 bits / ((Host_bit * 9) + (Remote_bit * 9) + FCdelay(1us) + BCCdelay(12us)).
But the example in App notes is for UB913/914. What is FC delay and BCC delay for UB962 with UB935?
I saw typical latency is 1.5us for 50MHz BC case at "Table 10. Back Channel GPIO Typical Timing" in UB962 datasheet. So BCC delay is 1.5us?
"7.4.11.3 Forward Channel GPIO" in UB962 datasheet said "The minimum latency for the GPIO remains consistent (approximately 225 ns)," so FC delay is 225ns?
If so , if both host side and remote side (camera) I2C are 400KHz, final throughput is slight less than 200KHz?
Does it mean both host side and remote side (camera) can operate at 400KHz but both should support clock stretch to reduce effective throughput to less than 200KHz?
And I2C mode "standard/fast/fast-plus" is only for local I2C access or for remote I2C access?
For above 400KHz I2C for both host side and remote side (camera) scenario, is it "standard" I2C mode? I set 0x0A/0x0B "SCL HIGH/LOW TIME" register to value 0x7A. Is it correct?
Looking forwarding your suggestion.
Great thanks