DP83849I: rise time requierement to reset and power down pins

Hi Ali,

We don't have a spec for power down pin rise time in this datasheet. How will this information be used?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hello Lucas, 

as described before, the dual function/Interrupt pin of the PHY is in my application simply pulled high, the reset pin is also pulled high but after power on this reset pin is released by the drain terminal of a FET. So the question is what maximum value for the pull up resistors is allowed. What is the maximum rise time? The larger the pull up value is the more time passes until the signal changes from low to high. Usually for inputs of a chip a rise time is given in datasheets.

Hi Ali,

We're looking into your question and will get back to you by Wednesday.

Thanks,

Lucas

Hi Ali,

Do you specifically need the reset rise time, or the time it takes for the PHY to stabilize after reset is released? The post RESET Stabilization time prior to MDC preamble for register accesses is 3 us maximum.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hello,

I need a recommendation for the maximum rise time in units e.g. [ns/V] so I can determine the maximum value of the pull-up resistor.

Hi Ali,

We're looking into this and will get back to you by Friday.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Ali,

Unfortunately, we don't characterize the rise time of the reset pin. We do however characterize the input low and high voltages VIL and VIH if these are useful. They can be found in Table 4.5 of the datasheet.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

OK thanks,

So summing up it doesnt matter if the voltage level of reset and power down pins are rising up e.g. through a 1k, 10k or 33k resistor from 0V towards VDD.