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TCA9555：I2C rise/fall time requirement

Akihiko Suzuki
Prodigy 20 points
Part Number: TCA9555

The clock frequency of I2C is designed at 327kHz.
In I2C BUS—FAST MODE, the AC specs of t_icr and t_icf are up to 300ns in the data sheet, but I think this value is the value when f_scl is up to 400kHz.

What I want to check is, as f_scl becomes a frequency slower than 400kHz, does the maximum value of t_icr and t_icf become larger than 300ns?
Also, when f_scl is 327kHz, what is the maximum value of t_icr and t_icf?　(If there is a relational expression between f_scl, t_icr, and t_icf, please let me know.)

f_scl: I2C clock frequency , t_icr: I2C input rise time , t_icf: I2C input fall time

  • 0
    TI__Guru 74262 points

    Suzuki-san,

    An engineer has been notified of this thread and will respond by tomorrow. Thank you for your patience.

    Regards,

    Eric Hackett

  • 0
    TI__Guru 73181 points

    Hello Akihiko,

    The terms you used: f_scl: I2C clock frequency , t_icr: I2C input rise time , t_icf: I2C input fall time

    come from the I2C standard which we included in the datasheet but does not actually define the requirement for our device. It only defines the system level spec'd you should target for your I2C system. Again, I am pointing out this is a system level spec and not a device level spec. 

    For our device (TCA9555) we use voltage thresholds to know the state of the SDA/SCL pins (not edge rate thresholds) so as long as you go below 30% of Vcc and above 70% of Vcc, then the rise and fall times of the system will work for our device. This means you could have a slower rise time/fall time then what the I2C system specs and still have it work with our device as long as you meet the 30% 70% thresholds. So if you wanted to operate at 327kHz and violate the rise/fall times spec'd by I2C, the device will still function/operate if you hit the threshold values. 

    Does this explanation help?

    -Bobby