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DP83867E: DP83867 Clocking question

Guangyan Liu
Intellectual 2130 points
Part Number: DP83867E

Dear Expert .

Good day!

Our customer are planning to use the DP83867 PHY and want to use the RX recovered clock from the device to be the master clock input into an FPGA using the CLK_OUT from the PHY to be able to run the FPGA synchronously with the recovered clock.  Can you provide information on how the CLK_OUT works when programmed for outputting the RX_CLK and set for 100 Mbps operation with 25 MHz CLK_OUT frequency?  For instance,

1. What is on the CLK_OUT pin when the Ethernet link is not set up yet?  Is the CLK_OUT a free running 25Mhz signal in that case? 

2. What happens to the CLK_OUT when the link is up and the recovered RX clock is available?  Does the CLK_OUT become synchronous with the recovered clock and is it a graceful switchover?

BR,

Leon.liu

  • 0
    TI__Guru**** 191119 points

    Hello Leon liu, 

    Thank you for the query.

    Please refer to the below section.

    8.3.3 Clock Output

    The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The local reference clock acts as the central source for all clocking in the device. The local reference clock is embedded into the transmit network packet traffic and is recovered from the network packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream and is locked to the transmit clock in the partner. Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input. The default output clock is suitable for use as the reference clock of another DP83867 device. Through registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.

    Hardware reset should not be performed on the PHY.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Intellectual 2130 points

    Dear  Sreenivasa

    Thank you for your reply ,

    The customer had seen that section in the data sheet but it isn’t clear how the recovered RX clock works when the Ethernet link is not up yet.

     Since they want to run their FPGA synchronous with the recovered RX clock they need to know if the RX clock will be active at 25Mhz on power up prior to the Ethernet link being up and the recovered clock being available.  Does the RX clock output initially output the 25Mhz synchronous with the input free running clock and then gracefully switch over to the RX recovered clock when the recovered clock is available?

     

    They are planning on using the RX recovered clock as the input to the PLL in our FPGA to generate the master clocks for the FPGA logic synchronous to the RX clock.  If the RX clock output is not active until after the link is up or the frequency and stability of it not guaranteed then the FPGA will never start since the FPGA controls the PHY chip.

    BR,

    Leon .liu

  • 0 in reply to Guangyan Liu
    TI__Guru**** 191119 points

    Hello Leon liu, 

    When the link is not up, the PHY will output the generated internal clock.

    Once the link is up, the PHY switches by itself to its recovered clock based on the register setting.

    I am not sure if this would be a completely graceful and could have some ump during transition.

    Would customer be open to using a jitter cleaner. 

    Regard,

    Sreenivasa