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DP83TG720EVM-MC: PMA Conformance Test Issues

Part Number: DP83TG720EVM-MC

Hi,

I was conducting PMA conformance tests for the DP83TG720R Media Converter board.

I consistently faced failures in PMA conformance tests in:

  • master jitter
  • slave jitter
  • Tx distortion

I have attached my test results.DP83TG720.zip

I have actually also check the test setup using other DUTs (from other manufacturers). I can get a pass results.

I have been using these test scripts file (see attachments) to set master and slave modes, and corresponding test modes.

begin

//Master Mode Configuration 
//Hard reset
000D 001f
000E 001f
000D 401f
000E 8000

//to not let the phy start the link-up procedure
//( till full configuration is written)
000D 001f
000E 0573
000D 401f
000E 0101

//to configure phy in master mode
//(if not done through straps already)
000D 0001
000E 0834
000D 4001
000E c001

//DSP settings for margins during OA EMC MDI
//emission test
000D 001f
000E 0405
000D 401f
000E 5800

//DSP settings for margins during OA EMC
//level-4 immunity test
000D 001f
000E 08ad
000D 401f
000E 3c51

000D 001f
000E 0894
000D 401f
000E 5df7

000D 001f
000E 08A0
000D 401f
000E 09e7

000D 001f
000E 08c0
000D 401f
000E 4000

000D 001f
000E 0814
000D 401f
000E 4800

000D 001f
000E 080d
000D 401f
000E 2ebf

000D 001f
000E 08c1
000D 401f
000E 0b00

000D 001f
000E 087d
000D 401f
000E 0001

000D 001f
000E 082e
000D 401f
000E 0000

000D 001f
000E 0837
000D 401f
000E 00f4

000D 001f
000E 08be
000D 401f
000E 0200

000D 001f
000E 08c5
000D 401f
000E 4000

000D 001f
000E 08c7
000D 401f
000E 2000

000D 001f
000E 08b3
000D 401f
000E 005a

000D 001f
000E 08b4
000D 401f
000E 005a

000D 001f
000E 08b0
000D 401f
000E 0202

000D 001f
000E 08b5
000D 401f
000E 00ea

000D 001f
000E 08ba
000D 401f
000E 2828

000D 001f
000E 08bb
000D 401f
000E 6828

000D 001f
000E 08bc
000D 401f
000E 0028

000D 001f
000E 08bf
000D 401f
000E 0000

000D 001f
000E 08b1
000D 401f
000E 0014

000D 001f
000E 08b2
000D 401f
000E 0008

000D 001f
000E 08ec
000D 401f
000E 0000

000D 001f
000E 08c8
000D 401f
000E 0003

000D 001f
000E 08be
000D 401f
000E 0201

//to bring phy out of non-autonomous mode
//( only if phy is strapped in non-auto mode)
000D 001f
000E 018c
000D 401f
000E 0001

//soft reset
000D 001f
000E 001f
000D 401f
000E 4000

//to let phy start the link-up procedure
//(after above configuration is done)
000D 001f
000E 0573
000D 401f
000E 0001

//to start the send-s detection during link-up
//sequence
000D 001f
000E 056a
000D 401f
000E 5f41

end
begin

//Master Mode Configuration 
//Hard reset
000D 001f
000E 001f
000D 401f
000E 8000

//to not let the phy start the link-up procedure
//( till full configuration is written)
000D 001f
000E 0573
000D 401f
000E 0101

//to configure phy in slave mode
//(if not done through straps already)
000D 0001
000E 0834
000D 4001
000E 8001

//DSP settings for margins during OA EMC MDI
//emission test
000D 001f
000E 0894
000D 401f
000E 5df7

//DSP settings for margins during OA EMC
//level-4 immunity test
000D 001f
000E 056a
000D 401f
000E 5f40

000D 001f
000E 0405
000D 401f
000E 5800

000D 001f
000E 08ad
000D 401f
000E 3c51

000D 001f
000E 0894
000D 401f
000E 5df7

000D 001f
000E 08a0
000D 401f
000E 09e7

000D 001f
000E 08c0
000D 401f
000E 4000

000D 001f
000E 0814
000D 401f
000E 4800

000D 001f
000E 080d
000D 401f
000E 2ebf

000D 001f
000E 08c1
000D 401f
000E 0b00

000D 001f
000E 087d 
000D 401f
000E 0001

000D 001f
000E 082e
000D 401f
000E 0000

000D 001f
000E 0837
000D 401f
000E 00f4

000D 001f
000E 08be
000D 401f
000E 0200

000D 001f
000E 08c5
000D 401f
000E 4000

000D 001f
000E 08c7
000D 401f
000E 2000

000D 001f
000E 08b3
000D 401f
000E 005a

000D 001f
000E 08b4
000D 401f
000E 005a

000D 001f
000E 08b0
000D 401f
000E 0202

000D 001f
000E 08b5
000D 401f
000E 00ea

000D 001f
000E 08ba
000D 401f
000E 2828

000D 001f
000E 08bb
000D 401f
000E 6828

000D 001f
000E 08bc
000D 401f
000E 0028

000D 001f
000E 08bf
000D 401f
000E 0000

000D 001f
000E 08b1
000D 401f
000E 0014

000D 001f
000E 08b2
000D 401f
000E 0008

000D 001f
000E 08ec
000D 401f
000E 0000

000D 001f
000E 08c8
000D 401f
000E 0003

000D 001f
000E 08be
000D 401f
000E 0201

//to avoid send-s detection till the configuration is
//done
000D 001f
000E 056a
000D 401f
000E 5f40

//to bring phy out of non-autonomous mode
//( only if phy is strapped in non-auto mode)
000D 001f
000E 018c
000D 401f
000E 0001

//soft reset
000D 001f
000E 001f
000D 401f
000E 4000

//to let phy start the link-up procedure
//(after above configuration is done)
000D 001f
000E 0573
000D 401f
000E 0001

//to start the send-s detection during link-up
//sequence
000D 001f
000E 056a
000D 401f
000E 5f41

end
begin
//100BASE-T1 PMA Test Control Register
// enabling test mode 1
000D 0001
000E 0904
000D 4001
000E 2000
//Read
000D 0001
000E 0904
000D 4001
000E
end
begin
//1000BASE-T1 PMA Test Control Register
// enabling test mode 4
000D 0001
000E 0904
000D 4001
000E 8000
000D 001F
000E 0453
000D 401F
000E 0019
//Read
000D 0001
000E 0904
000D 4001
000E
000D 001F
000E 0453
000D 401F
000E
end

Is there any possible configurations required? Or the DP83TG720R media converter is a suitable candidate to perform these tests?

Please help.

  • Just to add on the MASTER and SLAVE configurations are according to the application notes snla371a as attached:snla371a.pdf

  • Hello Teik Hooi Teoh, 

    Thank you for the query and inputs.

    Can i assume you are using TI EVM ?

    Please refer to the below document 

    https://www.ti.com/lit/pdf/snla371

    Regards,

    Sreenivasa

  • Yes as I have mentioned in my posts above, I was using the TI dp83tg720r media converter board. I also have referred to the application note that you have mentioned.

    Any additional details that I may have overlooked or did not do right?

  • Hello Teik Hooi Teoh, 

    Noted and thank you. Let me look it the data and get back to you by Tuesday or Wednesday. 

    Regards,

    Sreenivasa 

  • Hello Teik Hooi Teoh, 

    Could you please check with customer on the below 

    • Which SW customer is using for PMA compliance (i.e. Tek, Keysight, R&S, Lecroy).
    • What is the cable attachment they use to connect EVM to test fixture

    Can you also please check the below 

    master mode jitter test the sequence is as following : load the master mode script -> load the test mode 1 script -> No reset after that -> measure clkou

    Is there any other activity on the board while measuring the jitter and distortion? Is data being transferred from RJ45 to automotive connector ?For distortion testing is the clock from clkout used (divided by external board) for measurement?

    Regards,

    Sreenivasa

  • Hi,

    We are using Tektronix's Automotive Ethernet conformance test suite, based on latest version 1.4.2.1

    In master & slave jitter tests, Tektronix test setup requires DUT to have a link partner.

    So does link partner need to be configured using the slave / master mode script?

    Basically we follow to the steps you have described, no other activity after the configuration setup.

    No RJ45 connection. 

    The clkout signal is connected via a SMA cable with SMA-to-BNC converter to feed to scope channel.

    For distortion test, we are using Tektronix's software signal correction for external ref clock input.

    This is the default option for Tektronix and we have pass results for other DUTs that we have tested previously.

    We will be trying out the hardware clock divider option.

    We are also checking with Tektronix for possible setup improvements.

  • Hello Teik Hooi Teoh, 

    Thank you for the detailed inputs.

    On question on the other DUTs that you tested -was this a custom board or EVMs ?

    Did you follow similar approach for those boards.

    Regards,

    Sreenivasa

     

  • Hello Teik Hooi Teoh, 

    Good morning.

    How is the progress on the testing and your interaction with Tektronix.

    Regards,

    Sreenivasa

  • Hi I have been working with Tektronix and there are mixed results.

    For master / slave jitter tests, able to resolve. It was mainly due to the fact that TI EVM's CLKOUT is single ended while the Tektronix test application is expecting a differential clock signal, which happens to be implemented by other manufacturers.. This causes improper signal level during measurement acquisition. Manual adjustment has be made during the measurement and we could get pass results.

    As for the tx distortion test, we could not see any abnormal symptom from the scope measurement and test application settings. We consistently see all  fail results for all measurement points. We tried on two EVM boards and the results are similar. Are there any settings or adjustments that we can further explore regarding to this? Please help.

  • Hello Teik Hooi Teoh, 

    Thank you for the update.

    Are you powering the board from an USB or using external supply. For distortion test TI recommends using external supply.

    Can you please capture a couple of measurements and share the results.

    Regards.

    Sreenivasa

  • Hello Teik Hooi Teoh, 

    Did you have chance to perform some additional tests.

    Regards,

    Sreenivasa

  • Yes. Have been tested using external supply input with an benchtop adjustable DC supply source. Tried with 5V/7.5V/12V but all still produce similar results, the results still fails the TX distortion.

    Is there a detail test report for the tx distortion test? We are using Tektronix conformance test suite but probably there are reference or small details that we can refer to the test setup that TI has been using. 

    Is it possible to share with us the detail setup of the test that probably will show us some information on the below:

    • test steps and configurations for the DUT
    • test equipment, test fixture and test setup connection to DUT

    Please help to advice. Thanks!

  • Hello Teik Hooi Teoh, 

    Thank you for the inputs.

    Can you please share the results  that you are currently seeing.

    Can you also please share details on the setup that you are using for me to get it validaed.

    Regards,

    Srenivasa

  • Hi,

    So perhaps I will share more of the settings of the Tektronix setup.

    Basically I was following to Tektronix 1000BASE-T1 conformance test suite.

    I am using a Tektronix scope MSO64 with the 1000BASE-T1 Automotive Ethernet PMA test suite.

    I attach the document here for your reference.

    TekExpress-Automtoive-Ethernet-100BASE-T1-1000BASE-T1t-OnlineHelp=3=Traditional_US_Letter_PDF=EN-US_077088106.pdf

    The setup you can refer to this picture:

    The DUT is powered by a 7.5V AC adapter connected to the EVM's DC jack.

    DUT ground is also connected to the scope GND port as recommended in the Tektronix document.

    The DUT configurations are set via USB-2 MDIO Tool, with the below test scripts:

    begin
    
    //Master Mode Configuration 
    //Hard reset
    000D 001f
    000E 001f
    000D 401f
    000E 8000
    
    //to not let the phy start the link-up procedure
    //( till full configuration is written)
    000D 001f
    000E 0573
    000D 401f
    000E 0101
    
    //to configure phy in master mode
    //(if not done through straps already)
    000D 0001
    000E 0834
    000D 4001
    000E c001
    
    //DSP settings for margins during OA EMC MDI
    //emission test
    000D 001f
    000E 0405
    000D 401f
    000E 5800
    
    //DSP settings for margins during OA EMC
    //level-4 immunity test
    000D 001f
    000E 08ad
    000D 401f
    000E 3c51
    
    000D 001f
    000E 0894
    000D 401f
    000E 5df7
    
    000D 001f
    000E 08A0
    000D 401f
    000E 09e7
    
    000D 001f
    000E 08c0
    000D 401f
    000E 4000
    
    000D 001f
    000E 0814
    000D 401f
    000E 4800
    
    000D 001f
    000E 080d
    000D 401f
    000E 2ebf
    
    000D 001f
    000E 08c1
    000D 401f
    000E 0b00
    
    000D 001f
    000E 087d
    000D 401f
    000E 0001
    
    000D 001f
    000E 082e
    000D 401f
    000E 0000
    
    000D 001f
    000E 0837
    000D 401f
    000E 00f4
    
    000D 001f
    000E 08be
    000D 401f
    000E 0200
    
    000D 001f
    000E 08c5
    000D 401f
    000E 4000
    
    000D 001f
    000E 08c7
    000D 401f
    000E 2000
    
    000D 001f
    000E 08b3
    000D 401f
    000E 005a
    
    000D 001f
    000E 08b4
    000D 401f
    000E 005a
    
    000D 001f
    000E 08b0
    000D 401f
    000E 0202
    
    000D 001f
    000E 08b5
    000D 401f
    000E 00ea
    
    000D 001f
    000E 08ba
    000D 401f
    000E 2828
    
    000D 001f
    000E 08bb
    000D 401f
    000E 6828
    
    000D 001f
    000E 08bc
    000D 401f
    000E 0028
    
    000D 001f
    000E 08bf
    000D 401f
    000E 0000
    
    000D 001f
    000E 08b1
    000D 401f
    000E 0014
    
    000D 001f
    000E 08b2
    000D 401f
    000E 0008
    
    000D 001f
    000E 08ec
    000D 401f
    000E 0000
    
    000D 001f
    000E 08c8
    000D 401f
    000E 0003
    
    000D 001f
    000E 08be
    000D 401f
    000E 0201
    
    //to bring phy out of non-autonomous mode
    //( only if phy is strapped in non-auto mode)
    000D 001f
    000E 018c
    000D 401f
    000E 0001
    
    //soft reset
    000D 001f
    000E 001f
    000D 401f
    000E 4000
    
    //to let phy start the link-up procedure
    //(after above configuration is done)
    000D 001f
    000E 0573
    000D 401f
    000E 0001
    
    //to start the send-s detection during link-up
    //sequence
    000D 001f
    000E 056a
    000D 401f
    000E 5f41
    
    end
    
    begin
    //1000BASE-T1 PMA Test Control Register
    // enabling test mode 4
    000D 0001
    000E 0904
    000D 4001
    000E 8000
    000D 001F
    000E 0453
    000D 401F
    000E 0019
    //Read
    000D 0001
    000E 0904
    000D 4001
    000E
    000D 001F
    000E 0453
    000D 401F
    000E
    end
    

    Before the test, calibration steps are carried out as per the Tektronix document:

    The test results is as attached:

    Please help to validate and further advice on possible options that we can further explore.

  • Sorry the test result was missed out.

    Please see attached:DP83TG720R_006.zip

  • Hello Teik Hooi Teoh, 

    Thank you for the inputs.

    We will review the inputs and come back to you.

    Regards,

    Sreenivasa

  • Hi,

    If possible would TI also share the details in the test setup that TI has been conducted just for this test? For our references and comparison purposes.

    • equipment used
    • test application used
    • test fixture used
    • PHY configuration settings
  • Hello Teik Hooi Teoh, 

    Thanks for the message. Let me check and come back to you by end of the week.

    Regards,

    Sreenivasa

    .

  • Hello Teik Hooi Teoh, 

    Ar you using the 125MHz clock for testing. Please see below and let me know if you have the divider fixture that you could use for testing.

    Regards,

    Sreenivasa

  • Hello Teik Hooi Teoh, 

    Do you have some inputs for me.

    Regards,

    Sreenivasa

  • Hello Teik Hooi Teoh, 

    Do you have some inputs for me. Should i close the thread?

    Regards,

    Sreenivasa

  • Hi,

    Sorry for late reply. We tested base don the hardware clock divider and we got pass results.

    So it seems that the Tektronix software option has some discrepancies with the hardware option.

    If your side has any similar feedbacks from other customers, do share with us.

    Thanks!

  • Hello Teik Hooi Teoh, 

    Thank you for the update.

    We sometimes see that customer do not follow the recommended programming steps.

    What was the configuration you tested.

    Regards,

    Sreenivasa

  • Hello Teik Hooi Teoh, 

    I assume you configured the device in maser mode during the test.

    I will close the thread and thank you for all the inputs you have provided.

    Regards,

    Sreenivasa