DS90UB948-Q1: What if I wrongly reverse the port 0 and port 1, does the panel will show the right pattern

Hi Zirui,

Let me try to elaborate to ensure that we are at the same page. Basically, customer was connecting the port from 947 assuming SER 947 PORT0 -> DES 948 PORT1 and SER 947 PORT1 -> DES 948 PORT0. If this is the case, yes the video data will be corrupted since you are using dual links.

I think for single port, there is an option where you can reassignment the port.

Hope this helps. Let me know if you have further questions.

Aaron

Hi Aaron

Yes your understanding is right. Now customer has encountered the strange phenomenon that when they connect 949 (SER ) port 0 to 948 port 1 and connect 949 port 1 to 948 port 0, the display is also normal. Then they switch the connection of SERDES port, connect 949 port 0 to 948 port 0 and connect 949 port 1 to 948 port 1, the display is normal too. Could you please help look in to this strange phenomenon and using 949 and 948 EVM to do the test since in my opinion the display will be abnormal when we wrongly connect 949 port 0 to 948 port 1 and the IIC pass through may be also wrong while now the phenomenon seems everything is ok. Thank you.

Hi Zirui,

Can you provide me both schematic for 947 and 949?

Aaron

Hi Aaron,

If they mismatch the port0 and port1 from the UB948 side, will this damage the video image? But right now it seems working normally.

Question:

1. How does 949 FPD-LINK TX compress the image into two port? 

2. Could we change the Reg0x5C bit7 and 0x5B bit6 to swap the UB949 FPD TX port?

Thanks. 

Hi Aaron

Sorry the 949 side schematic I have not got since it is confidential. Here is the 948 schematic for you to review:

FCC C095_Schematic_948-LVDS_20201530.pdf

Besides, in addition to James' questions, what risks of IIC control signal communication due to the inverse connection? Some of the main control information is set passing through LVDS0 by default, we are afraid of there may be abnormalities or risks during initialization or hot swap. Thank you.

Hi Zirui, James,

Let me look into this, and I will get back with you by 8/5.

Aaron

Hi Aaron

Have you had any feedback to us? I search for the 949 datasheet and it said that in register 0x5B and 0x5C I suspect if the issue caused by the 0x5C bit[7]=0, so that even if the port wrongly connected, the display will be also normal, what is your suggestion and opinion? Thank you.

Hi Zirui,

Sorry for the delayed. As far as I know, the serializer and deserializer ports can't be swapped. They must be connected to PORT0 -> PORT0 and PORT1 -> PORT1. Let me discuss with my team, and I will get back with you by 8/11.

Aaron

Hi Aaron,

Hope you could provide us some solid information about the port connection issue. Here we have additional questions and updates for the issue:

1. In 949 datasheet, I'm confused about the function and description of 0x5C register. In function it said "DISABLE_DUAL_SWAP" while in description it said "Setting this bit allows writes to the DUAL_SWAP control……".

 "Setting this bit" means set the bit from 0 to 1? The default value 0 means disable dual swap or enable dual swap?

2. In customer previous configuration at 949 side, the 0x5B bit[0] and 0x5C bit[7] set as default values which are both 0;

Now we have told customer to modify the 0x5B bit[0] and 0x5C bit[7] to 1, while the display also work normally. Therefore, need your confirm by 8/11 that what risk or issue may occur when customer wrongly connect 949 port 0 to 948 port1 and 949 port 1 to 948 port 0, this issue related to that whether customer need to re design the schematic, thank you.

Hi Aaron

Any update for the validation and checking result? We are waiting for the evaluation of the wrongly connection potential risks and confirm, thank you.

Hi Aaron

Have you got some information with your team that the reason why port 0 must connected to port 0 and port1 to port 1? Customer is worried about modifying the hardware and need our confirm asap, thank you.

Casey, Aaron, 

Could you help to provide some feedbacks for this?

Customer is pushing for the clear answer from us.

Thanks. 

Hi Casey

So is it possible that: 

Customer previous configuration at 949 side, the 0x5B bit[0] and 0x5C bit[7] set as default values which are both 0——the display is normal, as well as we have told customer to modify the 0x5B bit[0] and 0x5C bit[7] to 1, while the display also work normally？

Hi Zirui,

Did your customer try with 947? Does it have the same issue?

Aaron

Hi Aaron

I think customer has not tried the 947 since their HU side using 949. So could you please help look into the 949-948 connection and in our 949 register configuration we try 2 sets:

A. 0x5B bit[0]=0 and 0x5C bit[7]=0

B. 0x5B bit[0]=1 and 0x5C bit[7]=1

The display will work normally either. That would confuse both of us and customer. 

Hi Zirui,

I need to setup the hardware and test this. I will get back with you by 8/25.

Aaron

Hi Zirui,

I would like to inform you that I was able to replicate the issue. When I swapped the hardware or configuring the register doesn't reflect anything. I am still getting lock and display patgen.

I am currently discussion my team. I will inform you once I have any results.

Aaron

Hi Aaron

Thanks for your information, may be your team could help to analyze it and give us some feedbacks, thank you.

Hi Zirui,

I had a discussion with my team. If you swap the ports of the part, it will automatically detect the swap. This is done internally.

If I manually swap the ports in dual mode, all I am doing is changing the order of even/odd pixel. This is what we expected behavior here.

Aaron