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DP83620: DP83620_Timing Clariifications

Srikanth Kacchu1
Expert 1255 points
Part Number: DP83620

Hi Team

We are using DP83620 in our design for MII interface. We could able to meet the trace length of 6inches for MII with zero margin.

Can we able to meet the timings for all the transactions? What is the turn around time of this PHY?

Regards

Srikanth Kacchu

  • 0
    TI__Guru**** 191239 points

    Hello Srikanth Kacchu

    Thank you for the query. What do you mean by zero margin ?

    What do you mean by turn around time of the PHY on the MII side?

    Have you considered series terminations, have you also matched the TX group signals and the RX group signals ?

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Expert 1255 points

    Hi Sreenivasa

    I mean, zero margin means I have utilized the maximum tracelength recommended for MII interface signals i.e, I have routed MII signals for 6 inches.

    As per MII standard, TX_DATA is transmitted from MAC to PHY on TX_CLK trigger on rising edge at MAC. On what basis, 6 inches is recommended for max MII tracelength?

    How fast MAC is assumed to transmit data on TX_CLK input? I meant this is the turn around time.

    Hope you understand. Please clarify.

    Regards

    Srikanth Kacchu

  • 0 in reply to Srikanth Kacchu1
    TI__Guru**** 191239 points

    Hello Srikanth,

    Thanks for the inputs.

    Please see below. 

    Recommended Maximum Trace Length 

    Although RMII and MII are synchronous bus architectures, there are a number of factors limiting signal trace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as cross talk. It is recommended to keep the signal trace lengths as short as possible. Ideally, keep the traces under 6 inches. Trace length matching, to within 2.0 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues. As with any high speed data signal, good design practices dictate that impedance should be maintained and stubs should be avoided throughout the entire data path.

    The MII clock is 25 MHz for 100M.

    The MII interface trace length dependency is on both the PHY and the MAC. You might want to also check the MAC capabilities.

    I assume you have the series terminations in place and following the guidelines to match the TX group traces and RX group traces.

    Regards,

    Sreenivasa