DS90UH948-Q1: Need 6 LVDS lanes

Lenio Cacula

Part Number: DS90UH948-Q1
Other Parts Discussed in Thread: DS90UB947-Q1

My customer requires 6 LVDS lanes (5 data pairs + 1 CLK pair) to transmit over about 5-foot cable. Do we have a Serializer/Deserializer that can carry these 6 lanes in a single chip? Data rate is about 800Mbps.

Thank you!

over 4 years ago

0 Hamzeh Jaradat over 4 years ago

TI__Guru** 108100 points

Hello Lenio,

I am not sure how this should work, i.e. which type of bit mapping over 5 data lanes?

using our DS90Ux948-Q1 you can chose either single oLDI mode (4 data lanes + 1 CLK) or dual oLDI mode (8 data lanes + 1 CLK). If you chose dual, you will have signal on all 8 data lanes, so you need to know which kind of bit mapping is required by your SoC or Display and connect the correct data lanes.

0 Lenio Cacula over 4 years ago in reply to Hamzeh Jaradat

TI__Genius 16700 points

This is not for a display application, but for communicating between a image sensor and a FPGA - we have some flexibility as far as mapping. I'd need something with higher data rate (800 Mbps). Do you know of any alternatives besides the DS90Ux948/947? We need both ends, serializer and deserializer, again with 5 or more lanes.

Thank you!

+1 Hamzeh Jaradat over 4 years ago in reply to Lenio Cacula

TI__Guru** 108100 points

Is your interface oLDI or you have flexibility here as well?

If the Interface is oLDI, then these are the only SER-DES options.

0 Lenio Cacula over 4 years ago in reply to Hamzeh Jaradat

TI__Genius 16700 points

It needs to be LVDS on both input and output, 800Mbps, over 5' cable. Those are the only hard requirements.

0 Casey McCrea over 4 years ago in reply to Lenio Cacula

TI__Guru** 103215 points

Hello Lenio,

LVDS is a broad sweeping term. Can you please be more specific in the type of LVDS solution you are looking for? Is it "OLDI" type LVDS which uses the 7 bits per clock cycle format (see DS90UB947-Q1 datasheet for an example).

Best Regards,

Casey

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DS90UH948-Q1: Need 6 LVDS lanes