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DP83867E: Shorting Maganment Bus of 2 ethernet PHY's and driving from FPGA

Divya Jyothi1
Intellectual 270 points
Part Number: DP83867E
Other Parts Discussed in Thread: TIDA-00204

Hi Support team,

We have 2 Ethernet ports which are connected to FPGA through 2# DP83867 Ethernet phy with SGMII interface.

Due to IO shortage at FPGA side, Planned to short MDC of PHY1 to PHY2  & MDIO of PHY1 to PHY2 and connected to FPGA. Same like I2C multi slave device connection to the Master.

Is this above concept will work ?

regards,

Divya

  • 0
    TI__Guru**** 190219 points

    Hello Divya, 

    Thank you for the query.. Please refer to the below section in the datasheet for details.

    8.4.2 Serial Management Interface

    Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used. During power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address. The DP83867IRPAP 64-pin variant can support up to 32 PHYs and uses a 5-bit address.

    As a reference you might want to reference to TIDA-00204.

    Please provide provision for terminations following the above referenced TI reference design.

    Regards,

    Sreenivasa