Dear Sir,
We need your assistance to clarify about frequency domain insertion loss/ return loss.
Our application is 933+ 954 , we want to confirm the insertion loss and return loss specification of the FPD-LINK .
1.We check the table 227 of DS90UB954-Q1 specification , it defined value of RL & IL. That is only for UB954 or can be the standard specification for all serializer & deserializer ?
2. Table 227 of DS90UB954-Q1 specification seems just defined for PCB trace only.
We want to know the insertion loss limit value (max) from DS90UB933 to DS90UB954 ( including TX PCB trace loss + connector loss+cable loss + connector loss + RX PCB trace loss)
In other words, about insertion we want to know the accepted decade value (max) from TX (PCB trace) -->connector -->cable--> connector--> (PCB trace) RX
3. We want to the know the return loss limit value of TX (DS90UB933).
4. If we need to inquiry the channel-Requirements-ADAS chipsets Limit line if TX+ RX are other different collocation.
Thank you.
