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NS16C2552: Effect of sampling timing deviation

Shinichi Inoue
Guru 21761 points
Part Number: NS16C2552


Dear Specialists,

My customer is evaluating NS16C2552 and has questions.

I would be grateful if you could advise.

---

According to the data sheet
UART reception has an internal sampling clock that is 16 times the data rate and
This sampling clock states that the data is sampling at 6/16 to 7/16 points of each bit.

We use data: 8bit, start bit: 1bit, stop bit 1bit, and parity for a total of 11bit.

Assuming that the sampling point deviates from the nominal sample point by 0.5ΔT, if this data is received continuously for 4 bytes,
1) Resynchronize the sampling clock for each start bit
→ Max deviation is (11-0.5) x ΔT
2) Synchronize the sampling clock only for the first start bit
→ The deviation of max is (44-0.5) x ΔT
Which one will it be?

Is your answer the same for PC16552.

---

I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Guru 74801 points

    Hi Shinichi,

    UARTs are generally supposed to do option 1, where they resync at the start bit assuming they sampled the stop bit. We don't have the design database for the devices you've asked about but generally if you had the second option, it would be fairly obvious as you would see signal integrity start to fall apart as you send more bytes of data continuously.

    -Bobby