NS16C2552: Specification of CLK duty cycle

Shinichi Inoue said:

About NS16C2552
(1)Is a 2kΩ pull-up required when using an external oscillator?
Is it the same for PC16552?

The pull up resistor value or any components on the xtal pins only depend on the crystal loading requirement, the UART device should be treated as independent from the oscillator requirments for the most part (you can use the parasitic cap loading in your crystal oscillator loading calculations.

Shinichi Inoue said:

(2) Regarding NS16C2552,Oscillation frequency; 18.432MH has been confirmed,
The rising edge of the oscillation waveform rises quickly, but the falling waveform is gentle.
I am checking the falling waveform.

Can you provide a scopeshot for us to see?

Shinichi Inoue said:

Is there a standard for duty ratio?

Normally the duty ratio is 50-50, I haven't seen one with a huge skew from that before.

Shinichi Inoue said:

If there is a duty ratio standard, is it the same for PC16552?

I would recommend the same duty cycle for both devices. 

Shinichi Inoue said:

In the case of such a waveform, it is expected that it is used in a situation where the DYTY ratio varies.
Is there a  possibility that communication will be poor if the sampling shifts little by little?

I would need to see how bad the shifts are. 

-Bobby

Hi Bobby,

Thank you for your reply.

I would reconfirm, could you please advise.

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About question (1), 

the customer uses external oscillator, not crystal unit.

In this case, my understanding, external resistor is not needed.

On the other hand, crystal oscillator needs to be considered with loading parasitic capacitance.

Is it correct?

Regarding question(2), could you please provide duty cycle tolerance.

In the customer's case,  CLK:H is 53%, CLK:L is 47%.

Is there any problem?

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I appreciate your great help and cooperation.

Best regards,

Shinichi

Shinichi Inoue said:

On the other hand, crystal oscillator needs to be considered with loading parasitic capacitance.

Is it correct?

Correct, usually the datasheet for the oscillator will provide some kind of expected cap loading and you can keep this value in mind with the parasitic capacitance of the XTAL pins.

Shinichi Inoue said:

Regarding question(2), could you please provide duty cycle tolerance.

In the customer's case,  CLK:H is 53%, CLK:L is 47%.

Is there any problem?

This is pretty close to 50% duty cycle. I don't believe this will generate any kind of issues.

I just want to verify though, does the scopeshot of the external oscillator look okay? (no clipping and the signal swings from 0V to Vcc)

*Also, what Baudrate is the customer trying to support or intend to use?

-Bobby

Hi Bobby,

Thank you for your reply.

Yes, I asked the customer to provide the clock waveform.

I'll share this when I could obtain.

I appreciate your great help and cooperation.

Best regards,

Shinichi