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Original question:

TCAN4550-Q1: How can set at 8Mbps data rate?

TCAN4550-Q1: Correct Bit timing for 8Mbps data rate

Sven2Mo
Prodigy 20 points
Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Hello,

a while ago someone asked how to set the bit timing on the TCAN4550 for a data rate of 8Mbps. There was a final answer given and the thread is closed, but the answer doesn't match the description in the TCAN45xx Software User's Guide.

According to the forum thread the bit timing shall be set as follows, assuming a 40MHz clock and a sample point of 80% (The given values are not the register values, that are one less of course):

Bit Rate Prescaler: 1
Time Segment Before Sample Point: 3
Time Segment After Sample Point: 2
Synchronization Jump Width: 2

But according to the Software User's Guide the synchronization segment of 1 time quanta must be considered as well. That means the values above result in a bit time of 6 time quanta's and a data rate of 6.67Mbps. Considering the synchronization segment the bit timing would be:

Bit Rate Prescaler: 1
Time Segment Before Sample Point: 3
Time Segment After Sample Point: 1
Synchronization Jump Width: 1

Can someone clarify which settings are correct? Does the "Time Segment Before Sample Point" on the TCAN4550 includes the synchronization segment or not?

Thank you in advance.

Regards
Sven

  • 0
    TI__Guru 53515 points

    Hi Sven,

    Good observation here. You are right that with the inclusion of the sync bit, the allocation of the Prop+Phase1 and Phase 2 segments would be as you described. However, to simplify calculations for those that don't read the user's guide as closely as you, the Time Segment Before Sample Point variable (DataTqBeforeSamplePoint in the demo code) includes the sync segment as well. This way, the time quanta (tq) in both of these variables will add up to be our divisor to calculate data rate. In the demo code, you will actually see that the DataTqBeforeSamplePoint variable is clamped to a minimum of 2 before it is written (before conversion to register values, that are one less of course).

    I'll also note that the solution you suggest does end up with a different sampling point if we assume the extra time quanta for the sync bit ends up before the sample point. The previous suggestion samples 3/5 (60%) the way through the bit-time where as your allocation would be 4/5 (80%) which may be more desirable for some systems. 

    Let me know if this is clear or if there's anything else I can comment on. 

    Regards,
    Eric Schott

  • 0 in reply to Eric Schott1
    Prodigy 20 points

    Hello Eric,

    thank you for your detailed answer and the clarification. That helps with our setup.

    There is one question left. The register description in the data sheet of the TCAN4550 (Revision C) restricts the value for the Time Segment Before and After Sample Point. For both variables the minimum register value is 1, respectively 2 when converting to the real value.

    This restriction is described for the nominal bit timing (register 0x101C) but not for the data bit timing (register 0x100C). And in the TI demo code this restriction is not considered as well.

    Our question is now does this restriction applies? Because if yes, our setup with 8Mbps and 80% sample point will not work. In this setup the Time Segment After Sample Point is 1, leading to a not allowed register value of 0. As consequence a sample point of 60% is required, with a Time Segment After Sample Point of 2 (register value 1).

    8Mbps, 80% Sample Point
    Bit Rate Prescaler: 1
    Time Segment Before Sample Point: 3
    Time Segment After Sample Point: 1
    Synchronization Jump Width: 1

    8Mbps, 60% Sample Point
    Bit Rate Prescaler: 1
    Time Segment Before Sample Point: 2
    Time Segment After Sample Point: 2
    Synchronization Jump Width: 2

    Can you please comment on the value restriction.

    Thank you in advance.

    Regards
    Sven

  • 0 in reply to Sven2Mo
    TI__Guru 53515 points

    Hi Sven,

    Good observation here, this is something I had not noticed before. You're right. Because of the restriction here, the minimum After Sample Point value will be 2tq. This is also reflected in the sample code as it checks that the input value is in range 2-257 before writing for both Pre- and Post-sample tq values (before adjusting for register value).  This would indeed limit an 8Mbps configuration to only sample at 60%. 

    I am checking with our team to see the reason for this limit. I'll get back to you with more info if anything develops or my response is determined inaccurate. 

    Regards,
    Eric Schott

  • 0 in reply to Eric Schott1
    Prodigy 20 points

    Hello Eric,

    thank you for your answer and your effort trying to help us.

    We had a detailed look in the TCAN4550 demo code (Version 1.2.2, 6/8/2020) and the timing settings are not as clear as you mentioned. Here is what we found in the code:

    Nominal Bit Timing
    Pre-Sample Allowed Values: 2-257
    Pre-Sample Register Values: 0-255
    Pre-Sample Datasheet: 1-255
    Post-Sample Allowed Values: 2-128
    Post-Sample Register Values: 1-127
    Post-Sample Datasheet: 1-127

    Data Bit Timing
    Pre-Sample Allowed Values: 2-33
    Pre-Sample Register Values: 0-31
    Pre-Sample Datasheet: not specified
    Post-Sample Allowed Values: 1-16
    Post-Sample Register Values: 0-15
    Post-Sample Datasheet: not specified

    So, from the demo code a register value of 0 maybe allowed for the data bit timing.

    Regards
    Sven

  • +1 in reply to Sven2Mo
    TI__Guru 53515 points

    Hi Sven,

    The timing configurations have two different data structs for each (nominal and data) rate; Simple, and Raw. The simple definition let's you define real values which the code will then convert to proper register values before writing to the device. The Raw definition expects register-ready data to be passed into it so these conversions must be done prior. This is why the ranges do no align, but the size of the range should be the same.

    The minimum value of the Nom Pre-sample raw data looks wrong here though. Because this struct reflects actual register data, the range should align with what's defined in the datasheet (1-255). This ensures that the sync and prop1 segments both have min values of 1. The device behavior with a zero written here is undefined, so the datasheet definition should be followed here. 

    Regards,
    Eric Schott

  • 0 in reply to Eric Schott1
    Prodigy 20 points

    Hello Eric,

    thank you for your explanation. That means the demo code is (mostly) correct and can be taken as reference. So, for the nominal bit timing the minimum register value for Pre- and Post-sample is 1. But in the data bit timing a minimum register value of 0 is allowed for Pre- and Post-sample. With this definition a sample point of 80% at 8Mbps is possible.

    Thank you very much for your great support. That answers all our questions.

    Regards
    Sven