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DS90UB954-Q1: Black issue when change resolution from 1920*720 to 1280*720

Jiawei Hu1
Expert 5565 points
Part Number: DS90UB954-Q1

Fullscreen sync_ok.txt Download 
a:\> ti dump 3 0x60 0x00 0xff   
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[00]
Read [60] Addr [00] ------> [60]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[01]
Read [60] Addr [01] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[02]
Read [60] Addr [02] ------> [1E]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[03]
Read [60] Addr [03] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[04]
Read [60] Addr [04] ------> [DF]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[05]
Read [60] Addr [05] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[06]
Read [60] Addr [06] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[07]
Read [60] Addr [07] ------> [FE]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[08]
Read [60] Addr [08] ------> [1C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[09]
Read [60] Addr [09] ------> [10]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0A]
Read [60] Addr [0A] ------> [7A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0B]
Read [60] Addr [0B] ------> [7A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0C]
Read [60] Addr [0C] ------> [83]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0D]
Read [60] Addr [0D] ------> [09]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0E]
Read [60] Addr [0E] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0F]
Read [60] Addr [0F] ------> [7F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[10]
Read [60] Addr [10] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[11]
Read [60] Addr [11] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[12]
Read [60] Addr [12] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[13]
Read [60] Addr [13] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[14]
Read [60] Addr [14] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[15]
Read [60] Addr [15] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[16]
Read [60] Addr [16] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[17]
Read [60] Addr [17] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[18]
Read [60] Addr [18] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[19]
Read [60] Addr [19] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1A]
Read [60] Addr [1A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1B]
Read [60] Addr [1B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1C]
Read [60] Addr [1C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1D]
Read [60] Addr [1D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1E]
Read [60] Addr [1E] ------> [04]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1F]
Read [60] Addr [1F] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[20]
Read [60] Addr [20] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[21]
Read [60] Addr [21] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[22]
Read [60] Addr [22] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[23]
Read [60] Addr [23] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[24]
Read [60] Addr [24] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[25]
Read [60] Addr [25] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[26]
Read [60] Addr [26] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[27]
Read [60] Addr [27] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[28]
Read [60] Addr [28] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[29]
Read [60] Addr [29] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2A]
Read [60] Addr [2A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2B]
Read [60] Addr [2B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2C]
Read [60] Addr [2C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2D]
Read [60] Addr [2D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2E]
Read [60] Addr [2E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2F]
Read [60] Addr [2F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[30]
Read [60] Addr [30] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[31]
Read [60] Addr [31] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[32]
Read [60] Addr [32] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[33]
Read [60] Addr [33] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[34]
Read [60] Addr [34] ------> [40]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[35]
Read [60] Addr [35] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[36]
Read [60] Addr [36] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[37]
Read [60] Addr [37] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[38]
Read [60] Addr [38] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[39]
Read [60] Addr [39] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3A]
Read [60] Addr [3A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3B]
Read [60] Addr [3B] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3C]
Read [60] Addr [3C] ------> [14]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3D]
Read [60] Addr [3D] ------> [6F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3E]
Read [60] Addr [3E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3F]
Read [60] Addr [3F] ------> [40]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[40]
Read [60] Addr [40] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[41]
Read [60] Addr [41] ------> [A7]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[42]
Read [60] Addr [42] ------> [71]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[43]
Read [60] Addr [43] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[44]
Read [60] Addr [44] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[45]
Read [60] Addr [45] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[46]
Read [60] Addr [46] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[47]
Read [60] Addr [47] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[48]
Read [60] Addr [48] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[49]
Read [60] Addr [49] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4A]
Read [60] Addr [4A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4B]
Read [60] Addr [4B] ------> [12]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4C]
Read [60] Addr [4C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4D]
Read [60] Addr [4D] ------> [33]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4E]
Read [60] Addr [4E] ------> [ED]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4F]
Read [60] Addr [4F] ------> [64]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[50]
Read [60] Addr [50] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[51]
Read [60] Addr [51] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[52]
Read [60] Addr [52] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[53]
Read [60] Addr [53] ------> [04]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[54]
Read [60] Addr [54] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[55]
Read [60] Addr [55] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[56]
Read [60] Addr [56] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[57]
Read [60] Addr [57] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[58]
Read [60] Addr [58] ------> [1E]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[59]
Read [60] Addr [59] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5A]
Read [60] Addr [5A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5B]
Read [60] Addr [5B] ------> [30]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5C]
Read [60] Addr [5C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5D]
Read [60] Addr [5D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5E]
Read [60] Addr [5E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5F]
Read [60] Addr [5F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[60]
Read [60] Addr [60] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[61]
Read [60] Addr [61] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[62]
Read [60] Addr [62] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[63]
Read [60] Addr [63] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[64]
Read [60] Addr [64] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[65]
Read [60] Addr [65] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[66]
Read [60] Addr [66] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[67]
Read [60] Addr [67] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[68]
Read [60] Addr [68] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[69]
Read [60] Addr [69] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6A]
Read [60] Addr [6A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6B]
Read [60] Addr [6B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6C]
Read [60] Addr [6C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6D]
Read [60] Addr [6D] ------> [7C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6E]
Read [60] Addr [6E] ------> [88]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6F]
Read [60] Addr [6F] ------> [88]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[70]
Read [60] Addr [70] ------> [2B]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[71]
Read [60] Addr [71] ------> [2C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[72]
Read [60] Addr [72] ------> [E4]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[73]
Read [60] Addr [73] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[74]
Read [60] Addr [74] ------> [D0]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[75]
Read [60] Addr [75] ------> [0F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[76]
Read [60] Addr [76] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[77]
Read [60] Addr [77] ------> [C5]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[78]
Read [60] Addr [78] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[79]
Read [60] Addr [79] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7A]
Read [60] Addr [7A] ------> [0F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7B]
Read [60] Addr [7B] ------> [DA]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7C]
Read [60] Addr [7C] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7D]
Read [60] Addr [7D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7E]
Read [60] Addr [7E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7F]
Read [60] Addr [7F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[80]
Read [60] Addr [80] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[81]
Read [60] Addr [81] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[82]
Read [60] Addr [82] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[83]
Read [60] Addr [83] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[84]
Read [60] Addr [84] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[85]
Read [60] Addr [85] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[86]
Read [60] Addr [86] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[87]
Read [60] Addr [87] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[88]
Read [60] Addr [88] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[89]
Read [60] Addr [89] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8A]
Read [60] Addr [8A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8B]
Read [60] Addr [8B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8C]
Read [60] Addr [8C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8D]
Read [60] Addr [8D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8E]
Read [60] Addr [8E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8F]
Read [60] Addr [8F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[90]
Read [60] Addr [90] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[91]
Read [60] Addr [91] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[92]
Read [60] Addr [92] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[93]
Read [60] Addr [93] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[94]
Read [60] Addr [94] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[95]
Read [60] Addr [95] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[96]
Read [60] Addr [96] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[97]
Read [60] Addr [97] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[98]
Read [60] Addr [98] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[99]
Read [60] Addr [99] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9A]
Read [60] Addr [9A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9B]
Read [60] Addr [9B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9C]
Read [60] Addr [9C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9D]
Read [60] Addr [9D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9E]
Read [60] Addr [9E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9F]
Read [60] Addr [9F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A0]
Read [60] Addr [A0] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A1]
Read [60] Addr [A1] ------> [0F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A2]
Read [60] Addr [A2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A3]
Read [60] Addr [A3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A4]
Read [60] Addr [A4] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A5]
Read [60] Addr [A5] ------> [1A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A6]
Read [60] Addr [A6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A7]
Read [60] Addr [A7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A8]
Read [60] Addr [A8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A9]
Read [60] Addr [A9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AA]
Read [60] Addr [AA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AB]
Read [60] Addr [AB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AC]
Read [60] Addr [AC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AD]
Read [60] Addr [AD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AE]
Read [60] Addr [AE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AF]
Read [60] Addr [AF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B0]
Read [60] Addr [B0] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B1]
Read [60] Addr [B1] ------> [14]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B2]
Read [60] Addr [B2] ------> [3F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B3]
Read [60] Addr [B3] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B4]
Read [60] Addr [B4] ------> [25]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B5]
Read [60] Addr [B5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B6]
Read [60] Addr [B6] ------> [18]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B7]
Read [60] Addr [B7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B8]
Read [60] Addr [B8] ------> [8C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B9]
Read [60] Addr [B9] ------> [33]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BA]
Read [60] Addr [BA] ------> [83]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BB]
Read [60] Addr [BB] ------> [74]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BC]
Read [60] Addr [BC] ------> [80]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BD]
Read [60] Addr [BD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BE]
Read [60] Addr [BE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BF]
Read [60] Addr [BF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C0]
Read [60] Addr [C0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C1]
Read [60] Addr [C1] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C2]
Read [60] Addr [C2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C3]
Read [60] Addr [C3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C4]
Read [60] Addr [C4] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C5]
Read [60] Addr [C5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C6]
Read [60] Addr [C6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C7]
Read [60] Addr [C7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C8]
Read [60] Addr [C8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C9]
Read [60] Addr [C9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CA]
Read [60] Addr [CA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CB]
Read [60] Addr [CB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CC]
Read [60] Addr [CC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CD]
Read [60] Addr [CD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CE]
Read [60] Addr [CE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CF]
Read [60] Addr [CF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D0]
Read [60] Addr [D0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D1]
Read [60] Addr [D1] ------> [43]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D2]
Read [60] Addr [D2] ------> [94]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D3]
Read [60] Addr [D3] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D4]
Read [60] Addr [D4] ------> [60]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D5]
Read [60] Addr [D5] ------> [F2]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D6]
Read [60] Addr [D6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D7]
Read [60] Addr [D7] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D8]
Read [60] Addr [D8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D9]
Read [60] Addr [D9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DA]
Read [60] Addr [DA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DB]
Read [60] Addr [DB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DC]
Read [60] Addr [DC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DD]
Read [60] Addr [DD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DE]
Read [60] Addr [DE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DF]
Read [60] Addr [DF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E0]
Read [60] Addr [E0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E1]
Read [60] Addr [E1] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E2]
Read [60] Addr [E2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E3]
Read [60] Addr [E3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E4]
Read [60] Addr [E4] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E5]
Read [60] Addr [E5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E6]
Read [60] Addr [E6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E7]
Read [60] Addr [E7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E8]
Read [60] Addr [E8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E9]
Read [60] Addr [E9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EA]
Read [60] Addr [EA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EB]
Read [60] Addr [EB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EC]
Read [60] Addr [EC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[ED]
Read [60] Addr [ED] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EE]
Read [60] Addr [EE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EF]
Read [60] Addr [EF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F0]
Read [60] Addr [F0] ------> [5F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F1]
Read [60] Addr [F1] ------> [55]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F2]
Read [60] Addr [F2] ------> [42]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F3]
Read [60] Addr [F3] ------> [39]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F4]
Read [60] Addr [F4] ------> [35]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F5]
Read [60] Addr [F5] ------> [34]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F6]
Read [60] Addr [F6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F7]
Read [60] Addr [F7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F8]
Read [60] Addr [F8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F9]
Read [60] Addr [F9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FA]
Read [60] Addr [FA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FB]
Read [60] Addr [FB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FC]
Read [60] Addr [FC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FD]
Read [60] Addr [FD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FE]
Read [60] Addr [FE] ------> [00]
a:\>
Fullscreen sync_ng.txt Download 
a:\> ti
Usage: ti [init|dump|read|write] [option]
       ti init <Channel>
       ti dump <Channel> <SalveAddr> <StartRegAddr> <TotalNum>
       ti read <Channel> <SalveAddr> <RegAddr>
       ti write <Channel> <SalveAddr> <RegAddr> data

For read TI953/TI954 Chip ID
       ti read 0x02 0x30 0x00 (expect 0x30)
a:\> ti dump 3 0x60 0x00 0xff
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[00]
Read [60] Addr [00] ------> [60]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[01]
Read [60] Addr [01] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[02]
Read [60] Addr [02] ------> [1E]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[03]
Read [60] Addr [03] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[04]
Read [60] Addr [04] ------> [DF]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[05]
Read [60] Addr [05] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[06]
Read [60] Addr [06] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[07]
Read [60] Addr [07] ------> [FE]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[08]
Read [60] Addr [08] ------> [1C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[09]
Read [60] Addr [09] ------> [10]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0A]
Read [60] Addr [0A] ------> [7A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0B]
Read [60] Addr [0B] ------> [7A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0C]
Read [60] Addr [0C] ------> [83]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0D]
Read [60] Addr [0D] ------> [09]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0E]
Read [60] Addr [0E] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[0F]
Read [60] Addr [0F] ------> [7F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[10]
Read [60] Addr [10] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[11]
Read [60] Addr [11] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[12]
Read [60] Addr [12] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[13]
Read [60] Addr [13] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[14]
Read [60] Addr [14] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[15]
Read [60] Addr [15] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[16]
Read [60] Addr [16] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[17]
Read [60] Addr [17] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[18]
Read [60] Addr [18] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[19]
Read [60] Addr [19] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1A]
Read [60] Addr [1A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1B]
Read [60] Addr [1B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1C]
Read [60] Addr [1C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1D]
Read [60] Addr [1D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1E]
Read [60] Addr [1E] ------> [04]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[1F]
Read [60] Addr [1F] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[20]
Read [60] Addr [20] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[21]
Read [60] Addr [21] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[22]
Read [60] Addr [22] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[23]
Read [60] Addr [23] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[24]
Read [60] Addr [24] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[25]
Read [60] Addr [25] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[26]
Read [60] Addr [26] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[27]
Read [60] Addr [27] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[28]
Read [60] Addr [28] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[29]
Read [60] Addr [29] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2A]
Read [60] Addr [2A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2B]
Read [60] Addr [2B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2C]
Read [60] Addr [2C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2D]
Read [60] Addr [2D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2E]
Read [60] Addr [2E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[2F]
Read [60] Addr [2F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[30]
Read [60] Addr [30] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[31]
Read [60] Addr [31] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[32]
Read [60] Addr [32] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[33]
Read [60] Addr [33] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[34]
Read [60] Addr [34] ------> [40]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[35]
Read [60] Addr [35] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[36]
Read [60] Addr [36] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[37]
Read [60] Addr [37] ------> [03]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[38]
Read [60] Addr [38] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[39]
Read [60] Addr [39] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3A]
Read [60] Addr [3A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3B]
Read [60] Addr [3B] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3C]
Read [60] Addr [3C] ------> [14]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3D]
Read [60] Addr [3D] ------> [6F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3E]
Read [60] Addr [3E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[3F]
Read [60] Addr [3F] ------> [40]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[40]
Read [60] Addr [40] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[41]
Read [60] Addr [41] ------> [A7]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[42]
Read [60] Addr [42] ------> [71]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[43]
Read [60] Addr [43] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[44]
Read [60] Addr [44] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[45]
Read [60] Addr [45] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[46]
Read [60] Addr [46] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[47]
Read [60] Addr [47] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[48]
Read [60] Addr [48] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[49]
Read [60] Addr [49] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4A]
Read [60] Addr [4A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4B]
Read [60] Addr [4B] ------> [12]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4C]
Read [60] Addr [4C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4D]
Read [60] Addr [4D] ------> [13]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4E]
Read [60] Addr [4E] ------> [3C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[4F]
Read [60] Addr [4F] ------> [64]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[50]
Read [60] Addr [50] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[51]
Read [60] Addr [51] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[52]
Read [60] Addr [52] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[53]
Read [60] Addr [53] ------> [04]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[54]
Read [60] Addr [54] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[55]
Read [60] Addr [55] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[56]
Read [60] Addr [56] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[57]
Read [60] Addr [57] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[58]
Read [60] Addr [58] ------> [1E]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[59]
Read [60] Addr [59] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5A]
Read [60] Addr [5A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5B]
Read [60] Addr [5B] ------> [30]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5C]
Read [60] Addr [5C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5D]
Read [60] Addr [5D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5E]
Read [60] Addr [5E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[5F]
Read [60] Addr [5F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[60]
Read [60] Addr [60] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[61]
Read [60] Addr [61] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[62]
Read [60] Addr [62] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[63]
Read [60] Addr [63] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[64]
Read [60] Addr [64] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[65]
Read [60] Addr [65] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[66]
Read [60] Addr [66] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[67]
Read [60] Addr [67] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[68]
Read [60] Addr [68] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[69]
Read [60] Addr [69] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6A]
Read [60] Addr [6A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6B]
Read [60] Addr [6B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6C]
Read [60] Addr [6C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6D]
Read [60] Addr [6D] ------> [7C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6E]
Read [60] Addr [6E] ------> [88]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[6F]
Read [60] Addr [6F] ------> [88]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[70]
Read [60] Addr [70] ------> [2B]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[71]
Read [60] Addr [71] ------> [2C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[72]
Read [60] Addr [72] ------> [E4]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[73]
Read [60] Addr [73] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[74]
Read [60] Addr [74] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[75]
Read [60] Addr [75] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[76]
Read [60] Addr [76] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[77]
Read [60] Addr [77] ------> [C5]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[78]
Read [60] Addr [78] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[79]
Read [60] Addr [79] ------> [01]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7A]
Read [60] Addr [7A] ------> [0B]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7B]
Read [60] Addr [7B] ------> [FF]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7C]
Read [60] Addr [7C] ------> [20]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7D]
Read [60] Addr [7D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7E]
Read [60] Addr [7E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[7F]
Read [60] Addr [7F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[80]
Read [60] Addr [80] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[81]
Read [60] Addr [81] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[82]
Read [60] Addr [82] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[83]
Read [60] Addr [83] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[84]
Read [60] Addr [84] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[85]
Read [60] Addr [85] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[86]
Read [60] Addr [86] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[87]
Read [60] Addr [87] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[88]
Read [60] Addr [88] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[89]
Read [60] Addr [89] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8A]
Read [60] Addr [8A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8B]
Read [60] Addr [8B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8C]
Read [60] Addr [8C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8D]
Read [60] Addr [8D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8E]
Read [60] Addr [8E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[8F]
Read [60] Addr [8F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[90]
Read [60] Addr [90] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[91]
Read [60] Addr [91] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[92]
Read [60] Addr [92] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[93]
Read [60] Addr [93] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[94]
Read [60] Addr [94] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[95]
Read [60] Addr [95] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[96]
Read [60] Addr [96] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[97]
Read [60] Addr [97] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[98]
Read [60] Addr [98] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[99]
Read [60] Addr [99] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9A]
Read [60] Addr [9A] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9B]
Read [60] Addr [9B] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9C]
Read [60] Addr [9C] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9D]
Read [60] Addr [9D] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9E]
Read [60] Addr [9E] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[9F]
Read [60] Addr [9F] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A0]
Read [60] Addr [A0] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A1]
Read [60] Addr [A1] ------> [0F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A2]
Read [60] Addr [A2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A3]
Read [60] Addr [A3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A4]
Read [60] Addr [A4] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A5]
Read [60] Addr [A5] ------> [1A]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A6]
Read [60] Addr [A6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A7]
Read [60] Addr [A7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A8]
Read [60] Addr [A8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[A9]
Read [60] Addr [A9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AA]
Read [60] Addr [AA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AB]
Read [60] Addr [AB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AC]
Read [60] Addr [AC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AD]
Read [60] Addr [AD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AE]
Read [60] Addr [AE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[AF]
Read [60] Addr [AF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B0]
Read [60] Addr [B0] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B1]
Read [60] Addr [B1] ------> [14]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B2]
Read [60] Addr [B2] ------> [3F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B3]
Read [60] Addr [B3] ------> [08]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B4]
Read [60] Addr [B4] ------> [25]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B5]
Read [60] Addr [B5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B6]
Read [60] Addr [B6] ------> [18]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B7]
Read [60] Addr [B7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B8]
Read [60] Addr [B8] ------> [8C]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[B9]
Read [60] Addr [B9] ------> [33]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BA]
Read [60] Addr [BA] ------> [83]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BB]
Read [60] Addr [BB] ------> [74]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BC]
Read [60] Addr [BC] ------> [80]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BD]
Read [60] Addr [BD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BE]
Read [60] Addr [BE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[BF]
Read [60] Addr [BF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C0]
Read [60] Addr [C0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C1]
Read [60] Addr [C1] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C2]
Read [60] Addr [C2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C3]
Read [60] Addr [C3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C4]
Read [60] Addr [C4] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C5]
Read [60] Addr [C5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C6]
Read [60] Addr [C6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C7]
Read [60] Addr [C7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C8]
Read [60] Addr [C8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[C9]
Read [60] Addr [C9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CA]
Read [60] Addr [CA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CB]
Read [60] Addr [CB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CC]
Read [60] Addr [CC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CD]
Read [60] Addr [CD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CE]
Read [60] Addr [CE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[CF]
Read [60] Addr [CF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D0]
Read [60] Addr [D0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D1]
Read [60] Addr [D1] ------> [43]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D2]
Read [60] Addr [D2] ------> [94]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D3]
Read [60] Addr [D3] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D4]
Read [60] Addr [D4] ------> [60]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D5]
Read [60] Addr [D5] ------> [F2]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D6]
Read [60] Addr [D6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D7]
Read [60] Addr [D7] ------> [02]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D8]
Read [60] Addr [D8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[D9]
Read [60] Addr [D9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DA]
Read [60] Addr [DA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DB]
Read [60] Addr [DB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DC]
Read [60] Addr [DC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DD]
Read [60] Addr [DD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DE]
Read [60] Addr [DE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[DF]
Read [60] Addr [DF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E0]
Read [60] Addr [E0] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E1]
Read [60] Addr [E1] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E2]
Read [60] Addr [E2] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E3]
Read [60] Addr [E3] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E4]
Read [60] Addr [E4] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E5]
Read [60] Addr [E5] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E6]
Read [60] Addr [E6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E7]
Read [60] Addr [E7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E8]
Read [60] Addr [E8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[E9]
Read [60] Addr [E9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EA]
Read [60] Addr [EA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EB]
Read [60] Addr [EB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EC]
Read [60] Addr [EC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[ED]
Read [60] Addr [ED] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EE]
Read [60] Addr [EE] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[EF]
Read [60] Addr [EF] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F0]
Read [60] Addr [F0] ------> [5F]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F1]
Read [60] Addr [F1] ------> [55]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F2]
Read [60] Addr [F2] ------> [42]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F3]
Read [60] Addr [F3] ------> [39]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F4]
Read [60] Addr [F4] ------> [35]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F5]
Read [60] Addr [F5] ------> [34]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F6]
Read [60] Addr [F6] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F7]
Read [60] Addr [F7] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F8]
Read [60] Addr [F8] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[F9]
Read [60] Addr [F9] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FA]
Read [60] Addr [FA] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FB]
Read [60] Addr [FB] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FC]
Read [60] Addr [FC] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FD]
Read [60] Addr [FD] ------> [00]
<DEBUG> Ti_RegRead Channel=[3] SlaveID=[60] Addr=[FE]
Read [60] Addr [FE] ------> [00]
a:\>

Hi team,

My customer use 953 and 954 in their DVR project, and now they met an black issue when change resolution from 1920*720 to 1280*720. The topology is as below:

Camera-UB953-UB954-SOC-927-928-display

Test have been done:

  • 954 lock is always high, but have no output when issue happen
  • 954 pattern of 1920*720 and 1280*720 is normal
  • Register dump of two resolutions, see attached

Could you kindly why this happen? Appreciate for your help!

  • 0
    TI__Mastermind 28380 points

    Hi Jiawei,

    If the 954 has lock (0x04[2] = HIGH), then the UB954 is receiving valid serial data. But I see that TX_PORT_PASS bit (0x35[0]) is not set in the failing 1280*720 configuration. Since you are using Round Robin forwarding, this bit indicates if the input traffic is being actively forwarded to the CSI-2 Tx output port.

    When the UB954 detects an error condition, the standard response is to flag this error and then not send the corrupted CSI-2 data downstream. When it recovers from the error condition, it will provide a Frame Start packet and resume sending valid data. See Section 7.5.9 in the UB954 datasheet for more information.

    Right now, I'm looking through your register dump to find the specific issue. I believe that an error condition is causing the data to not be forwarded and causing you to have a blank screen.

    In the meantime, could you try to perform a digital reset in the UB954 during the 1280*720 configuration, to see if this will clear any falsely-raised error flags? In register 0x01, set DIGITAL_RESET0 to 1. This bit is self-clearing and will reset the entire digital block, but not clear your register settings.

    Best,

    Justin Phan

  • 0 in reply to Justin Phan
    TI__Expert 5565 points

    Hi Phan,

    Understood it. I also think there an error in UB954 configuration. Reset UB954 doesn't work. So could you kindly help comparison register and give me some new debug directions?

    Thanks!

    BR

    Jiawei

  • 0 in reply to Jiawei Hu1
    TI__Mastermind 28380 points

    Hi Jiawei,

    In the UB954, I see that register 0x7C = 0x20. This means that the DISCARD_ON _PAR_ERR bit is set. However, since the PARITY_ERROR bit is not set in register 0x4D, this should not be causing the issue.

    In the UB954, I see that register 0x7D = 0x00. But since PASS_DISCARD_EN is not enabled, then frames will not be discarded based on the PASS status.

    Besides these points, I see a few discrepancies in the flagged error bits between the working and failing setup. After your 1280*720 setup stabilizes, could you try clearing the error bits that were set in registers 0x4D/4E/55/56/7A/7B? Also try clearing register 0x37 as well. These bits are cleared on read.

    Then, provide another register dump to see which error bits are still set.

    Best,

    Justin Phan