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DS90UB953-Q1: MIPI lines issue

FRANK1
Expert 8535 points
Part Number: DS90UB953-Q1

Hi sir,

I am using DS90UB953-Q1 for serializing video output and it uses MIPI CSI-II,

Now my question we are having very small place for routing serilizer and challenge is to make length matching between MIPI lines
So how much tolerance between MIPI lines is acceptable ?

and also wanted to know like how much timing tolerance is there between TWO MIPI lanes
How much pico seconds or nano seconds delay is acceptable between Two MIPI lane?
or what should be the MAX length difference is allowable for MIPI lane..

Thanks.

  • +1
    TI__Guru** 107460 points

    Hello Frank1,

    We recommend pair-to-pair (ex. Data to CLK) length matching should be within 25 mils, and intra-pair (P to N) length should be within 5 mils.

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 8535 points

    Hi Hamzeh,

    Thank you for your response.

    Could you give any timing details between two MIPI lanes or between clock and MIPI lanes so I can set length to match timing.
    (for an example....max time difference between two MIPI lane should be 20n.) 
    Thank you.
    Regards,
  • +1 in reply to FRANK1
    TI__Guru** 103215 points

    Hello Frank,

    The max allowable skew comes from the MIPI DPHY CTS. For 953 rates which go up to 832Mbps, the max allowable skew between each data lane and the clock is +/-0.15UI where the UI is the MIPI clock UI. But we always recommend as good design practice to minimize this skew as much as possible in the design to give the best margin for the design which may be degraded by any other factors such as external noise aggressors. 

    Best Regards,

    Casey