I am looking to communicate to a PCI Target Device through using a PCIe IP Core running on an FPGA with very low latency.
This is a relatively custom application, My question is with regards how off-the-shelf of a solution this is. I am looking to be able to send a message such as "write data 0x1234 at address 0xABCD" or "read from address 0xAAAA" in packet form through PCIe, send that too this bridge, and then have that say "write data 0x1234 at address 0xABCD" or whatever the message was on the PCI side(following the PCI spec), and have this device be relatively plug-and-play.
The architecture I am looking into is Primary FPGA=>PCIe-to-PCI-Bridge=> Target PCI Device, in which the target PCI device will never be or attempt to be bus master.
Essentially, I am looking to maybe provide some configuration for XIO2001, the necessary interface circuitry, and have the rest of the support lie on the PCIe development on the primary FPGA side, and the target PCI device development, but nothing else really required for bridge.
Would the XIO2001 help me achieve this goal? Or will there be custom driver development required for the XIO2001?
