• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 505 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TCAN1042V-Q1: TX/RX Waveform not followed well

Rocky Chen
Expert 8880 points
Part Number: TCAN1042V-Q1

Hi Expert,

We are using TCAN1042V. It is found sometime/occasionally the RX signal is not following TX signal, that caused system communication error.

Below is waveform and schematic, when changing to TJA1042TK/3, there is no this issue.

Could you help see this issue and give some suggestions?  Thank you!

TX-RX Waveform

- Rocky

  • 0
    TI__Guru 53575 points

    Hi Rocky,

    It is common for the RXD signal to be different from TXD when receiving data from the bus during arbitration and acknowledge portions of a CAN frame. However, whenever TXD is driving dominant (logic 0), this should also be represented on the bus (RXD should also be 0). This does not appear to be the case in the above waveforms. Please help with a bit more information. 

    • Please capture scope shots of the CAN bus (CANH and CANL) as well as the TXD signal of the problematic transceiver. This will help us see if the driver is responding correctly to the TXD signal and if it can properly drive the state of the CAN bus. 
    • Which signal is TXD and RXD in the above scope shots? 
    • When a CAN controller recognizes a discrepancy in frame format, it will send an error frame (6 consecutive dominant bits). Most controllers will also set some interrupt flag to indicate the nature of the error. Is it possible to check what interrupt is set in the CAN controller after this test? I suspect something like a Bit 0 Error was encountered: – Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive.
    • How many device exhibit this behavior? Is this the only test in which the unit appears to act in an unexpected manner?

    Regards,
    Eric Schott