Hello
we are producing LVDS data from FPGA and trying to supply to display panel.
Looks like we need physical layer change when we drive displays - CML logic
Now in TDP158, it seems, there is a 100Ohm termination, but i see common mode voltage of 0.7V
LVDS signals have common mode voltage of 1.2V.
As typical rating has been given in datasheet, my question is can TDp158 take 1.2V common mode with 400mV pk-pk swing as input.
Thanks
Atharva
