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DP83848K: A Question on Power Feedback Connection on PHY chip

Yuanchen Zhu
Intellectual 425 points

Part Number: DP83848K

Hello, everyone

  When referencing to AN-1469 PHYTER Design & Layout Guide, I am not quite sure on understanding of the part of power feedback connection, in Section4.1.  As I understand it from the document, PFBIN1 and 2 act as an internal regulator to supply power to PFBOUT pin, which essentially achieve the purpose of a power feedback network.  What I do not quite get is, about the Fig 10 shown in the document, it seems like we should tie PFBIN1 and 2 directly to PFBOUT first, the remaining capacs are placed parrallel to ground after the connection.  Plus, the placeholder order of 0.1uF and 10uF in the same figure bothers me, which makes the topology of capacs seem not to function as only filtering network for chip pins, but filtering for other purposes.  I can feel it, but I cannot clearly think it through. Hope someone can shed some light on it.

  Feel free to point out if I was not clear on the question.

  Thanks

Yuanchen Zhu

  • 0
    Intellectual 425 points

    Actually, along with writing out the confusion, I found out it should be the direction of PFBOUT to PFBIN1/2. But still confused. Should 10uF be place near to PFBOUT than 0.1uF, or is it just random order on sch and one should take care of it in actual layout for himself for a right order? 

  • +1 in reply to Yuanchen Zhu
    TI__Guru**** 223915 points

    Hello Yuanchen Zhu,

    Thank you for the query.

    Please see below extract from the datasheet.

    PFBOUT (O)  : Power Feedback Output. Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT.

    PFBIN1 PFBIN2 (I):  Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin.

    Note: Do not supply power to these pins other than from PFBOUT.

    To ensure correct operation for the DP83848x, parallel caps with values of 10 µF (Tantalum) and 0.1 µF should be placed close to pin 19 (PFBOUT) of the device. Pin 16 (PFBIN1) and pin 30 (PFBIN2) must be connected to pin 19 (PFBOUT), each pin requires a small capacitor (0.1 µF).

    In the design please place 0.1 uF + 10 uF close to the PFBOUT and 0.1 uF each near to PFBIN2. You can then route the traces from PFBOUT to PFBINX.

    If you have a design you are working, i can support a review to make it easy for you.

    Regards,

    Sreenivasa