TPS25750: How to execute PBMs

Part Number: TPS25750
Other Parts Discussed in Thread: USB2ANY,

In the "TPS25750 Host Interface Technical Reference Manual", PBMs have an ”I2C Slave Address” in Byte5. What address should I enter for this?
Is it TPS25750 own slave address?

Also,  Should I first write to DATA1 and then write ”PBMs” to CMD1?

  • Hi,

    As mentioned the I2C address is based on the ADCINx decoded value.

    See page 44 of the TPS25750 datasheet.

    You can refer to section 4 of the TPS25750 TRM for loading the patch flow.

    Regards.

  • After executing PBMs, 0x05 can be read in OUTPUT DATA (DATA1). Does this mean that the slave address of the TPS25750 has not been set correctly?

    I entered all patterns up to 0x01-0x3F for the slave address and tried it, but all returned 0x05.

    What do you think is wrong in this case?

  • Kobayashi-san,

    This flow is in the TRM document. If it's successful DATA1 should read 0.

    Did you read CMD1 after executing the PBMs? 

  • I read CMD1 and it is 0x00.

    The following is the log when register is set using USB2ANY.
    ---------------------------------------------------------------------------------------------------------------------------------
    2021-08-04 09:34:27.168 DebugLogging is Enabled
    2021-08-04 09:34:27.168 PacketLogging is Disabled
    2021-08-04 09:34:27.168 Profiling is Disabled
    2021-08-04 09:34:27.274
    2021-08-04 09:34:27.275 INFO: Packet logging is Disabled
    2021-08-04 09:34:27.276 INFO: Activity logging is Enabled
    2021-08-04 09:34:27.846 INFO: Target Power: 3.3v is OFF, 5.0v is OFF, Adj is OFF
    2021-08-04 09:34:27.972 INFO: Found 1 USB2ANY controller.
    2021-08-04 09:34:28.081 INFO: Opened USB2ANY S/N 2572435119000900 successfully!
    2021-08-04 09:34:28.097 INFO: Firmware Version: 2.8.2.0
    2021-08-04 09:34:28.144 INFO: Enabled EVM Detect interrupt handler
    2021-08-04 09:34:28.144 I2C: I2C bit rate set to 400 kHz.
    2021-08-04 09:34:28.159 I2C: I2C internal address size changed to 1 byte
    2021-08-04 09:34:28.159 I2C: I2C internal address changed to 00
    2021-08-04 09:37:23.231 SMBus: Slave Address changed to 0x21
    ■ Read INT_EVENT1.ReadyForPatch=1b
    2021-08-04 09:37:23.239 SMBus Read 0x0021 18 bytes Data: 0x0000: 0B 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 ................
    ■ Reead MODE='PTCH'
    2021-08-04 09:38:01.696 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 50 54 43 48 00 00 00 00 00 00 00 00 00 00 00 .PTCH...........
    ■ Write DATA1: bundle size=0x3780h, I2C Slave Address=0x21h, Timeout value=0x32h
    2021-08-04 09:41:56.665 SMBus Write 0x0021 8 bytes Data: 0x0000: 09 00 80 37 00 00 21 32 00 00 00 00 00 00 00 00 ...7..!2........
    ■ Read DATA1
    2021-08-04 09:42:08.440 SMBus Read 0x0021 8 bytes Data: 0x0000: 40 00 80 37 00 00 21 32 00 00 00 00 00 00 00 00 @..7..!2........
    ■ Write CMD1='PBMs'
    2021-08-04 09:43:12.215 SMBus Write 0x0021 5 bytes Data: 0x0000: 08 50 42 4D 73 00 00 00 00 00 00 00 00 00 00 00 .PBMs...........
    ■ Read CMD1=0h
    2021-08-04 09:43:24.533 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    ■ Read DATA1: PatchStartStatus=0x05h(Invalid slave address)
    2021-08-04 09:43:43.812 SMBus Read 0x0021 8 bytes Data: 0x0000: 40 05 80 37 00 00 21 32 00 00 00 00 00 00 00 00 @..7..!2........
    ---------------------------------------------------------------------------------------------------------------------------------

    ※TPS25750EVM settings
    ・Remove jumper(J4) to disable I2C flash boot.
    ・Input 20V to SYS_POWER(TP4).

  • I think your DATA1 write is not correct.

     09 00 80 37 00 00 21 32 00 00 00 00 00 00

    should be 09 80 37 00 00 21 32 00 00 00 00 00 00

  • I changed the setting of the DATA1 register you pointed out, but the result was the same.

    The log of USB2ANY is described.
    ---------------------------------------------------------------------------------------------------------------------------------
    2021-08-11 14:34:22.739 DebugLogging is Enabled
    2021-08-11 14:34:22.739 PacketLogging is Disabled
    2021-08-11 14:34:22.739 Profiling is Disabled
    2021-08-11 14:34:22.858
    2021-08-11 14:34:22.859 INFO: Packet logging is Disabled
    2021-08-11 14:34:22.859 INFO: Activity logging is Enabled
    2021-08-11 14:34:23.559 INFO: Target Power: 3.3v is OFF, 5.0v is OFF, Adj is OFF
    2021-08-11 14:34:23.656 INFO: Found 1 USB2ANY controller.
    2021-08-11 14:34:23.764 INFO: Opened USB2ANY S/N 2572435119000900 successfully!
    2021-08-11 14:34:23.779 INFO: Firmware Version: 2.8.2.0
    2021-08-11 14:34:23.840 INFO: Enabled EVM Detect interrupt handler
    2021-08-11 14:34:23.841 I2C: I2C bit rate set to 400 kHz.
    2021-08-11 14:34:23.855 I2C: I2C internal address size changed to 1 byte
    2021-08-11 14:34:23.856 I2C: I2C internal address changed to 00
    2021-08-11 14:34:30.757 SMBus: Slave Address changed to 0x21
    ■ Read INT_EVENT1.ReadyForPatch=1b
    2021-08-11 14:34:30.776 SMBus Read 0x0021 17 bytes Data: 0x0000: 0B 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 ................
    ■ Reead MODE='PTCH'
    2021-08-11 14:35:02.152 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 49 32 43 20 00 00 00 00 00 00 00 00 00 00 00 .I2C............
    ★ Write DATA1: bundle size=0x3780h, I2C Slave Address=0x21h, Timeout value=0x32h
    2021-08-11 14:35:38.385 SMBus Write 0x0021 7 bytes Data: 0x0000: 09 80 37 00 00 21 32 00 00 00 00 00 00 00 00 00 ..7..!2.........
    ■ Read DATA1
    2021-08-11 14:36:00.650 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 80 37 00 00 21 32 00 00 00 00 00 00 00 00 00 @.7..!2.........
    ■ Write CMD1='PBMs'
    2021-08-11 14:36:49.983 SMBus Write 0x0021 5 bytes Data: 0x0000: 08 50 42 4D 73 00 00 00 00 00 00 00 00 00 00 00 .PBMs...........
    ■ Read CMD1=0h
    2021-08-11 14:37:01.894 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    ■ Read DATA1: PatchStartStatus=0x05h(Invalid slave address)
    2021-08-11 14:37:16.551 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 05 37 00 00 21 32 00 00 00 00 00 00 00 00 00 @.7..!2.........
    ---------------------------------------------------------------------------------------------------------------------------------

  • The data read back from DATA1 is not matching with what you have written, It looks like your data size is too much 0x3705 vs. 0x3780.

  • Thank you for your answer.
    However, the problem has not been resolved.

    Isn't the reason why the DATA1 register changed from 0x3780h to 0x3705h is that the first byte of the OUTPUT DATA1 register changed to 0x05 (Invalid slave address) after writing "PBMs"
    to the CMD1 register?

    If there is a problem with the bundle size, isn't the first byte of the OUTPUT DATA1 register 0x04 (Invalid bundle size)?

    I understood that by looking at "Figure 4-1" and "3.3.1'PBMs' Start Patch Burst Mode Download Sequence" of the TPS25750 Host Interface Technical Reference Manual.
    Is my understanding wrong?

    The answer was that the bundle size was large, so I set it to 0x100h, but it became 0x105h.
    Does this mean that the bundle size is small?(There was no such explanation in the manual.)
    The log of USB2ANY is described.
    ---------------------------------------------------------------------------------------------------------------------------------
    2021-08-17 09:38:54.436 DebugLogging is Enabled
    2021-08-17 09:38:54.436 PacketLogging is Disabled
    2021-08-17 09:38:54.436 Profiling is Disabled
    2021-08-17 09:38:54.610
    2021-08-17 09:38:54.611 INFO: Packet logging is Disabled
    2021-08-17 09:38:54.612 INFO: Activity logging is Enabled
    2021-08-17 09:38:55.255 INFO: Target Power: 3.3v is OFF, 5.0v is OFF, Adj is OFF
    2021-08-17 09:38:55.318 INFO: Found 1 USB2ANY controller.
    2021-08-17 09:38:55.414 INFO: Opened USB2ANY S/N 2572435119000900 successfully!
    2021-08-17 09:38:55.430 INFO: Firmware Version: 2.8.2.0
    2021-08-17 09:38:55.493 INFO: Enabled EVM Detect interrupt handler
    2021-08-17 09:38:55.494 I2C: I2C bit rate set to 400 kHz.
    2021-08-17 09:38:55.497 I2C: I2C internal address size changed to 1 byte
    2021-08-17 09:38:55.498 I2C: I2C internal address changed to 00
    2021-08-17 09:39:06.915 SMBus: Slave Address changed to 0x21
    ■ Read INT_EVENT1.ReadyForPatch=1b
    2021-08-17 09:39:25.892 SMBus Read 0x0021 17 bytes Data: 0x0000: 0B 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 ................
    ■ Reead MODE='PTCH'
    2021-08-17 09:39:44.029 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 50 54 43 48 00 00 00 00 00 00 00 00 00 00 00 .PTCH...........
    ★ Write DATA1: bundle size=0x0100h, I2C Slave Address=0x21h, Timeout value=0x32h
    2021-08-17 09:40:04.184 SMBus Write 0x0021 7 bytes Data: 0x0000: 09 00 01 00 00 21 32 00 00 00 00 00 00 00 00 00 .....!2.........
    ■ Read DATA1
    2021-08-17 09:40:24.371 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 00 01 00 00 21 32 00 00 00 00 00 00 00 00 00 @....!2.........
    ■ Write CMD1='PBMs'
    2021-08-17 09:42:12.670 SMBus Write 0x0021 5 bytes Data: 0x0000: 08 50 42 4D 73 00 00 00 00 00 00 00 00 00 00 00 .PBMs...........
    ■ Read CMD1=0h
    2021-08-17 09:42:34.819 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    ■ Read DATA1: PatchStartStatus=0x05h(Invalid slave address)
    2021-08-17 09:42:56.831 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 05 01 00 00 21 32 00 00 00 00 00 00 00 00 00 @....!2.........
    ---------------------------------------------------------------------------------------------------------------------------------

    The fundamental question is, can I use the TPS25750EVM to update the patch bundle over the I2C bus?

  • I was looking at data read back if they are matching, but then the flow checkpoint is to see if data1 is = 0. Let me get back to you on this.

  • This process has confused several people in the past.

    The easiest way to understand it is that all writes and reads that involve the 4CC commands to the CMD1 and Data1 register (0x08 and 0x09) are made to the I2Cs address (0x21) in your case.

    The read that you have highlighted should be the 0x21 address.

    You have also configured the I2C address for the burst data to be the same as the I2Cs address.  This will not work

      Write DATA1: bundle size=0x0100h, I2C Slave Address=0x21h, Timeout value=0x32h
    2021-08-17 09:40:04.184 SMBus Write 0x0021 7 bytes Data: 0x0000: 09 00 01 00 00 21 32 00 00 00 00 00 00 00 00 00 .....!2.........

    This address must be different than the I2Cs address and any other device that is on the I2Cs bus.  I usually suggest 0x50 because it is almost always used for an EEPROM and there is not likely to be an EEPROM on the bus.

    I suggest that you change this line to: 

     Write DATA1: bundle size=0x0100h, I2C Slave Address=0x21h, Timeout value=0x32h
    2021-08-17 09:40:04.184 SMBus Write 0x0021 7 bytes Data: 0x0000: 09 00 01 00 00 50 32 00 00 00 00 00 00 00 00 00 .....!2.........

    If you do this, then use the 0x50 address for the bulk write of the C array for the low region binary and then follow the rest of the flow in the flow chart.

    This section commonly trips up customers.

  • Thank you for your answer.

    As you answered, I modified it to "I2C Slave Address=0x50h", and the DATA1 register became 0x00h (successful patch start).

    The log of USB2ANY.
    ---------------------------------------------------------------------------------------------------------------------------------
    2021-08-18 09:34:16.024 INFO: Packet logging is Disabled
    2021-08-18 09:34:16.025 INFO: Activity logging is Enabled
    2021-08-18 09:34:16.581 INFO: Target Power: 3.3v is OFF, 5.0v is OFF, Adj is OFF
    2021-08-18 09:34:16.705 INFO: Found 1 USB2ANY controller.
    2021-08-18 09:34:16.811 INFO: Opened USB2ANY S/N 2572435119000900 successfully!
    2021-08-18 09:34:16.842 INFO: Firmware Version: 2.8.2.0
    2021-08-18 09:34:16.894 INFO: Enabled EVM Detect interrupt handler
    2021-08-18 09:34:16.895 I2C: I2C bit rate set to 400 kHz.
    2021-08-18 09:34:16.923 I2C: I2C internal address size changed to 1 byte
    2021-08-18 09:34:16.924 I2C: I2C internal address changed to 00
    2021-08-18 09:36:24.233 SMBus: Slave Address changed to 0x21
    ■ Read INT_EVENT1.ReadyForPatch=1b
    2021-08-18 09:36:24.251 SMBus Read 0x0021 17 bytes Data: 0x0000: 0B 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 ................
    ■ Reead MODE='PTCH'
    2021-08-18 09:37:39.391 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 50 54 43 48 00 00 00 00 00 00 00 00 00 00 00 .PTCH...........
    ★ Write DATA1: bundle size=0x3780h, I2C Slave Address=0x50h, Timeout value=0x32h
    2021-08-18 09:38:34.931 SMBus Write 0x0021 7 bytes Data: 0x0000: 09 80 37 00 00 50 32 00 00 00 00 00 00 00 00 00 ..7..P2.........
    ■ Read DATA1
    2021-08-18 09:38:44.650 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 80 37 00 00 50 32 00 00 00 00 00 00 00 00 00 @.7..P2.........
    ■ Write CMD1='PBMs'
    2021-08-18 09:39:11.417 SMBus Write 0x0021 5 bytes Data: 0x0000: 08 50 42 4D 73 00 00 00 00 00 00 00 00 00 00 00 .PBMs...........
    ■ Read CMD1=0h
    2021-08-18 09:39:23.973 SMBus Read 0x0021 5 bytes Data: 0x0000: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    ★ Read DATA1: PatchStartStatus=0x00h(Patch start success)
    2021-08-18 09:39:33.912 SMBus Read 0x0021 7 bytes Data: 0x0000: 40 00 00 00 00 50 32 00 00 00 00 00 00 00 00 00 @....P2.........
    ---------------------------------------------------------------------------------------------------------------------------------

    The subsequent bulk write of the C array of low range binaries was also successful,
    and we were able to verify that the MODE register was changed to 'APP '.

    I really appreciate yours support.

  • Happy to be able to help you solve this issue.

    Please click the this resolves my issue once you are satisfied with your status.