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TUSB4020BI: Question about GRST and power switching mode

diverger
Expert 1275 points
Part Number: TUSB4020BI

I'm planning to use TUSB4020BI in my design. And I have several questions:

  1. The GRST require a minimum low duration of 3 ms. In the reference design tidrlt6, it simply place a 1uF capacitor on this pin, as there are already a pull-up in the chip, so I guess it combine with the pull-up in the chip to generate the delay. If so, is it safe to use 1uF capacitor in my design? And what's the value of the pull-up in the chip?
  2. I'm planning to use the chip without external configuration interfaces (no EEPROM and no SMBus) but with power switching function, such as overcurrent protection, is it possible?

Thanks.

  • 0
    TI__Guru 60870 points

    Hi,

    1. The pullup current range on GRSTz is defined in the datasheet.  1uF is sufficient for most applications.  If the voltage rail ramps are slow, a 2 uF cap could be used instead.

    2. EEPROM and SMBUS are not required for normal operation including power switching / overcurrent features.

    Regards,

    JMMN