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DS90UB941AS-Q1: DS90UB941AS-Q1+DS90UB926's issue

chen zh
Intellectual 300 points
Part Number: DS90UB941AS-Q1


Dear Ti:

       I met one issue:  UB941(single mode)->link0 UB926->480*480 display.  Display didn't work.

      

      At the same time, other 720*720's display can work. Please help check the following configuration, thanks:

        0x01, 0x02,
        0x01, 0x08,
        0x03, 0xda,  //enable crc, dsi clock, i2c passthrough mode
        0x12, 0x00, //i2s disable, video select 24-bit mode
        0x17, 0x9e,  //DATAPATH_CTL ,  I2C_CONTROL
        0x30, 0xc0, //reserved?
        0x40, 0x04, 0x41, 0x05, 0x42, 0x06, //DPHY_SKIP_TIMING 0x40
        0xc6, 0x00, // INT disable
        0x5b, 0x01, // force single mode
        0x01, 0x00,

  • 0
    TI__Guru** 103215 points

    Hello Chen,

    The 941 has a minimum PCLK range of 25MHz, so the above timing will not work unless the PCLK is increased to at least 25MHz 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Hi Casey:

        Thank you. It solve my doubt, and I've tried this way:

        UB941 input is 800*480, i cut it to 480*480 in 941 so that we can output 480*480 to link0. I found one qustion, why the PCLK still was 27M in UB926, it's been cutted into 480*480 and should be about 17M, right?  Because the display can't work in 27M, how does UB926 output  17M PCLK?

  • 0 in reply to chen zh
    TI__Guru** 103215 points

    Hello Chen,

    In this test, what is the DSI clock frequency going to the 941 input?

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Hi Casey:

          About 27M

  • 0 in reply to chen zh
    TI__Guru** 103215 points

    Hello Chen,

    I don't mean the video PCLK, I mean the DSI frequency 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Hi Casey:

          Ok...There are 4 lanes and 0x5f register value is 0x1a, so DSI lane freq is 27M*6=162Mbps.

         And i have applied the following configuration for cut the 800*480 to 480*480 and don't know if it could work in single mode.

    0x6a, 0x88, //hb_h,hs_h
    0x6b, 0x08, // hs_l
    0x6c, 0x32, // hb_l
    0x36, 0x00, // x position
    0x37, 0x80, // x enable
    0x38, 0xdf,
    0x39, 0x01,
    0x3a, 0x00,
    0x3b, 0x00,
    0x3c, 0xdf,
    0x3d, 0x01,
  • 0 in reply to chen zh
    TI__Guru** 103215 points

    Hello Chen,

    As I mentioned before, 941AS has a minimum PCLK of 25MHz per lane. So in this case where you are trying to split an image to two ports, your DSI input frequency must be at least 300Mbps. This configuration you are trying to achieve here is not working because you are well under the minimum PCLK range for the device 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Hi Casey:

         I use the single mode for this case and don't split operation.

        1. Because of PCLK limit, this chip can work if input frequency is more than 150Mbps, now there is   162Mbps, so 941AS DSI input should work;

         2. Since pattern 480*480 test is ok, so i think output 480*480 should be ok.

         3. We can cut 800*480 to 480*480 when in single mode?

        

  • 0 in reply to chen zh
    TI__Guru** 103215 points

    Hello Chen,

    There are two constraints that you need to meet. 

    1. The DSI input frequency must be > 150Mbps/lane 

    2. Each FPD-Link output PCLK frequency must be > 25Mhz 

    So if you do a split with 800x480 you may be able to meet the first requirement, but not the second. So the way to achieve this would be to increase the blanking of the video to meet both requirements 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Dear Casey:

          Okay... so now my question are:

         1. Why does 480*480 pattern mode test display normally and can output 17Mhz's pclk? 

         2. Why does 941AS output 27Mhz after cut 800*480 to 480*480?  Cut operation can't work in single mode? It should output 17Mhz if cut op work normally even display exist issue.

         It does puzzle me.

  • +1 in reply to chen zh
    TI__Guru** 103215 points

    Hello Chen,

    It is very difficult for us to predict the device's behavior when it is used outside of the way it was designed, specified, and validated. So I would strongly suggest we focus on a configuration which is actually within the device's specification and then debug from there. Even if 480x480 worked at 17Mhz for you, it is not a configuration we suggest using the device in to guarantee performance over PVT variation. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 300 points

    Hi Casey:

         Get it. Thanks again..

    BR,

    Arvin