DP83867IS: Couldn't see PHY at some power cycles

Hi Srinivas,

Can you clarify what you mean by "we didn't see the PHY"? Is the PHY not powering on, or is there no link detected? Can you probe RX_CLK and CLKOUT to see if they are present?

This could possibly be a POR timing issue. Can you confirm your supply ramps meet the datasheet requirements? This could also possibly be a strap contention issue. Can you share your schematic for review?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas,

Thanks for the reply.

"we didn't see the PHY" - I meant, processor didn't detect the PHY. It was powered on. The processor could able to detect only after a power cycle.

I will share the captures later today. I had shared the schematic - attaching here again.

Thanks,

Srinivas

1258.DP83867IS.pdf

Hi Srinivas,

My apologies, I didn't see the attachment in your original post. I'm reviewing your schematic and will provide feedback by Wednesday.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Srinivas,

Here are my notes after reviewing your schematic:

• I recommend using the following supplies decoupling caps as suggested in the datasheet:
• What ground isolation is there between erth gnd and phy gnd?
• Can you confirm the values of caps C165 and C166? Are they 8.2pF?
• Are you able to read/write registers? Typically we recommend no PU on MDC, but if you aren't having issues then your current configuration should be ok.
• Try using the following RC network on the reset pin so reset doesn't ramp before the supplies do.
• I recommend separately decoupling the magnetics center taps through ground rather than shorting them together.
• Are there DC blocking caps on SOP and SON?
• I have also reached out internally about JTAG termination, and will get back to soon with a recommendation on this.

This seems like a POR issue, so I recommend trying the reset network to see if this works. Can you share a diagram of supply ramps including reset? Can you read registers in both the working and nonworking cases?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Srinivas,

We recommend leaving the JTAG pins floating as opposed to pulling them down.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas,

Thanks for the comments .I will go through and let you know the observations.

A quick update - adding a reset from Processor  to PHY, after power-up we are not seeing the issue. We didn't implement the reset in software as the PHY datasheet didn't say it is a mandatory.

Regards,

Srinivas

Hi Srinivas,

Can you share a supply ramp diagram including the reset line?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas,

Please see below. Yellow: +3.3V_ETH and Green: RESET_N

Thanks,

Srinivas

Hi Srinivas,

Can you share an image with all supplies individually ramping as well as reset? It seems like since a reset is needed after powerup, reset is not rising after all supplies have ramped. Can you try the following RC network on the reset pin?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas,

As the POR is generated by PHY itself I believe the reset captured on the board doesn't  represent the POR generated by the PHY.

As the RESET_N pin has the pull up on the board, it is raising along with +3.3V_ETH.

Please see below power-up timing from the datasheet. It doesn't give any info on the POR.

Thanks,

Srinivas