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DS90UB941AS-Q1: DSI data to clock timing

Arie Li
Expert 3390 points
Part Number: DS90UB941AS-Q1

Hi Experts,

How to understand below DSI data to clock timing in datasheet page 17? Can you share a timing diagram with tsetup and thold defination? Why the sum of the max tsetup and thold is not equal to 1UI? Why the min value of tsetup and thold is a negative number? Thank you.

Arie

  • +1
    TI__Guru** 103215 points

    Arie,

    This comes directly from section 10.2.1 of the MIPI DPHY specification. But the way it is specified in the DS90UB941AS-Q1 datasheet is slightly confusing. Setup and hold times should not be negative. The timing budget defined in the spec is constructed to intentionally leave budget for the degradation of the signal across the interconnect between TX and RX 

    Best Regards,

    Casey