DP83869HM: More information on Built In Self Test (BIST)

Steven Ziegler

Part Number: DP83869HM

I am looking for more information on how to use Built In Self Test (BIST) on the DP83869HM.

What is the sequence of register writes to enable MII Loopback, use the PRBS generator, and the TX checker?
When using the PRBS generator, what is the packet size?
With reference to page 79 of dp83869hm.pdf, bits 7 and 8 of PRBS_TX_CHK_CTRL Register. There is a note saying “Writing bit 7 generates a lock signal for the PRBS TX counters. Writing bit 8 generates a lock and clear signal for the PRBS TX counters.” I am not sure exactly what it means by “lock and clear”. Does it mean to lock it at 0?
How do you disable the lock on the PRBS_TX_CHK_BYTE_CNT register after it has been locked by setting either bit 7 or 8 of the PRBS_TX_CHK_CTRL Register?

If there are any application notes or better documentation of how to use BIST, I would greatly appreciate it if you could send a link to me.

over 4 years ago

0 Vikram Sharma over 4 years ago

TI__Genius 16030 points

Hello Steven,

Thanks for reaching out. I am checking with the team if we already have an app note with further details. If not, then I will check it myself and send you the required details. It may take a day or two for me to get back on this. I hope that is ok.

Regards,

Vikram

0 Steven Ziegler over 4 years ago in reply to Vikram Sharma

Prodigy 10 points

Vikram,

Thanks for the response. Yes, that is fine. I look forward to your response.

Thanks,

Steven Ziegler

0 Vikram Sharma over 4 years ago in reply to Steven Ziegler

TI__Genius 16030 points

We dont have a dedicated app note with further details. I am confirming the asked details with design team and will get back.

Regards,

Vikram

0 Vikram Sharma over 4 years ago in reply to Vikram Sharma

TI__Genius 16030 points

Hello Steven,

1. For MII loopback : write register 0x0000[14] = 1. Do an extra write of register 0x0016 = x0004 if 100Base-Tx mode is used. During Mii loopback data is sent from the MAC side and received back by the MAC. PHY's internal data generator and checkers are not involved.

For other queries I am still following up for details and confirmation from design team and will keep you posted.

Regards,

Vikram

+1 Vikram Sharma over 4 years ago in reply to Vikram Sharma

TI__Genius 16030 points

Hello Steven,

Here are the other answers which you have been looking for:

Packet length is controlled by register 0x007B[15:0] and IPG is controlled by register 0x007C[7:0]
The lock signal latches the counter values to shadow registers for read back. Lock and clear with latch the counters to the shadow registers for read back and also clear the actual counters. Locking is disabled by returning the lock bits back to default.

Regards,

Vikram

0 Steven Ziegler over 4 years ago

Prodigy 10 points

Vikram,

Thanks for your response. That answers my initial questions.

I do have one additional question. What loopback modes can be used with the PRBS generator?

Thanks,

Steven Ziegler

0 Vikram Sharma over 4 years ago in reply to Steven Ziegler

TI__Genius 16030 points

PCS, digital and analog loopback.

0 Steven Ziegler over 4 years ago in reply to Vikram Sharma

Prodigy 10 points

Vikram,

Thank you.

Sorry, but I just thought of another question. Do the PRBS TX check counters work with all three of those loopback modes (PCS, digital and analog) as well?

Thanks,

Steven Ziegler

0 Vikram Sharma over 4 years ago in reply to Steven Ziegler

TI__Genius 16030 points

Steven,

Sure. Yes the prbs checker works with these loopbacks.

Regards,

Vikram

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DP83869HM: More information on Built In Self Test (BIST)