Hello TI Team,
just a quick clarification. In the datasheet, page 10, the note states:
The HD3SS3202 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
Does this mean that it is required to invert lane C0, if, for example B0 is already inverted? Or that B1 needs to be inverted if B0 is inverted?
In general, I do not understand this note in context with USB3 - wouldn't the host and device determine the correct lane polarities during link training, regardless if the other is swapped or not?
Thanks!
Daniels