Hello,
We are having difficulty using the DS90UB960 interfacing with a DS90UB953 (4G mode) serializer. We are not able to get a lock on the FPD-Link III signal. When using GPIO output for lock, we get the following:
Some system info:
- POC is present on the system but disabled by removing the first ferrite in the POC string and powering the camera externally.
- Caps used are 50V rated X7R, 0.1u on P, 0.047 on N.
- System status registers:
- 0x4D: 0x00
- 0x4E: 0x02
- 0x04: 0xD0
- PDB is coming up in userspace well after power is applied to part
- Sufficient speed cables are being used
- Oscillator is running at 25MHz, REFCLK_VALID is OK
- Noise on VDD_1V8 and VDD_1V1 interfaces is below 10mV at the part input
- RX_PORT_CTL (0x0C) has 0x0F
- BCC_CONFIG (0x58) has 0x1E
- We are using a POC strategy that has the via going through the board to POC components at the back. POC is disabled here. We have used this strategy before without incident, but the board is also slightly thicker than usual (85.2mil instead of 62mil)
Let me know if there's any additional information we can provide. We are also working to enable CMLOUT to take a look at the eye diagram. Any advice into additional values to check or adjust would be helpful.
Thank you,
Andrew Kowalczyk
