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TPS65988: Problems reading the flash memory

Daniels Kurgs
Prodigy 180 points
Part Number: TPS65988


Hello TI Team,

we recently fixed a hardware bug in our system where our TPS65988 as a PD source only on both ports was being back-powered due to some leakage (powered by the sink).

But now, with the correct power sequencing (user powers on system, 5V and 3.3V rails are generated, 3.3V supplies the 3.3V_LDO rail), the SPI flash is not correctly read, even though it was previously.

Our suspicions are on the flash data out signal pull-down R12 (SPI_POCI in the datasheet). With it removed (no pulldown or pulldown), the flash was able to be read in the abnormal power conditions. Now, it can't be read when R12 is open, 1k, 3k or 10k. 

The desired Boot config is BP_NoResponse Config1 (SPI_POCI =0, DIV=0.14)

Do you maybe have any ideas on the expected R12 value or see any other problems?

Thanks,

Daniels 

  • 0
    TI__Mastermind 29765 points

    Hi Daniels,

    Can you capture the SPI transaction? We normally recommend the pullup for SS and other pull resistors to be 3.3K and not so for pulldown. If you use pullup (SPI_POCI =1) in safe config do you see it working correctly?

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 180 points

    Hi pdjuandi,

    I was able to ''hack'' the functionality I need in a different configuration. Instead of BP_NoResponse/ Config1 I put the controller in the BP_ECWait_External/ Infinte Wait mode. (Since we don't have external load switches, the chip tries to enable them, but nothing happens, so it is like NoResponse)

    This was possible only with SPI_POCI =1 and DIV =0.54. As a pull-up I used 3k and 4.7k, both worked. 

    I could not enter this same mode with SPI_POCI=0. Pull-down values I tried were 3k, 4.7k and 56k. The flash has its output high voltage rated at a mere 100uA output current on its SO pin, so 56k should have worked.

    When I removed the pull-down and added the 4.7k pull-up back, the image was loaded successfully.

    In any case, I was able to obtain the needed functionality and sadly cannot dedicate any more time to soldering and testing to obtain the SPI comms. Sorry about that.

    To any engineers implementing the SPI communications, I would strongly advise taking one of the boot configurations which has SPI_POCI=1, it seems to be working at a wide range of resistor values.

    Regards,

    Daniels